JAJSGI1B November   2018  – May 2022 DLP4710

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
    14. 6.14 Software Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Low-Speed Interface
      3. 7.3.3 High-Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Optical Interface and System Image Quality
        1. 7.5.1.1 Numerical Aperture and Stray Light Control
        2. 7.5.1.2 Pupil Match
        3. 7.5.1.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On and Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Device Markings
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-AAEE7578-2F09-43E0-B6D0-225C9B3A244F-low.gif Figure 5-1 FQL Package. 100-Pin LGA. Bottom View.
Table 5-1 Connector Pins
PIN(1) TYPE SIGNAL DATA RATE DESCRIPTION PACKAGE NET LENGTH(2) (mm)
NAME NO.
DATA INPUTS
D_AN(0) G3 I SubLVDS Double Data, Negative 5.01
D_AN(1) F4 I SubLVDS Double Data, Negative 2.03
D_AN(2) E3 I SubLVDS Double Data, Negative 2.41
D_AN(3) E6 I SubLVDS Double Data, Negative 4.71
D_AN(4) J5 I SubLVDS Double Data, Negative 3.23
D_AN(5) L5 I SubLVDS Double Data, Negative 3.87
D_AN(6) G5 I SubLVDS Double Data, Negative 6.32
D_AN(7) L3 I SubLVDS Double Data, Negative 1.84
D_AP(0) H3 I SubLVDS Double Data, Positive 5.01
D_AP(1) G4 I SubLVDS Double Data, Positive 2.03
D_AP(2) E4 I SubLVDS Double Data, Positive 2.41
D_AP(3) E5 I SubLVDS Double Data, Positive 4.71
D_AP(4) J6 I SubLVDS Double Data, Positive 3.23
D_AP(5) L6 I SubLVDS Double Data, Positive 3.87
D_AP(6) G6 I SubLVDS Double Data, Positive 6.32
D_AP(7) L4 I SubLVDS Double Data, Positive 1.84
D_BN(0) G27 I SubLVDS Double Data, Negative 2.51
D_BN(1) E26 I SubLVDS Double Data, Negative 4.43
D_BN(2) D28 I SubLVDS Double Data, Negative 2.76
D_BN(3) D26 I SubLVDS Double Data, Negative 5.47
D_BN(4) L25 I SubLVDS Double Data, Negative 4.85
D_BN(5) K25 I SubLVDS Double Data, Negative 4.10
D_BN(6) L28 I SubLVDS Double Data, Negative 2.53
D_BN(7) K27 I SubLVDS Double Data, Negative 2.76
D_BP(0) F27 I SubLVDS Double Data, Positive 2.51
D_BP(1) E27 I SubLVDS Double Data, Positive 4.43
D_BP(2) D27 I SubLVDS Double Data, Positive 2.76
D_BP(3) D25 I SubLVDS Double Data, Positive 5.47
D_BP(4) L26 I SubLVDS Double Data, Positive 4.85
D_BP(5) J25 I SubLVDS Double Data, Positive 4.10
D_BP(6) K28 I SubLVDS Double Data, Positive 2.53
D_BP(7) J27 I SubLVDS Double Data, Positive 2.76
DCLK_AN J3 I SubLVDS Double Clock, Negative 3.77
DCLK_AP K3 I SubLVDS Double Clock, Positive 3.77
DCLK_BN H26 I SubLVDS Double Clock, Negative 2.98
DCLK_BP H27 I SubLVDS Double Clock, Positive 2.98
CONTROL INPUTS
LS_WDATA D3 I LPSDR (1) Single Write data for low speed interface. 1.20
LS_CLK C3 I LPSDR Single Clock for low-speed interface 1.20
DMD_DEN_ARSTZ B6 I LPSDR Asynchronous reset DMD signal. A low signal places the DMD in reset. A high signal releases the DMD from reset and places it in active mode. 4.19
LS_RDATA_A C6 O LPSDR Single Read data for low-speed interface 3.93
LS_RDATA_B C4 O LPSDR Single Read data for low-speed interface 2.57
POWER (3)
VBIAS B27 Power Supply voltage for positive bias level at micromirrors 24.51
VBIAS B4 Power 24.51
VOFFSET B2 Power Supply voltage for HVCMOS core logic. Supply voltage for stepped high level at micromirror address electrodes.
Supply voltage for offset level at micromirrors.		 49.56
VOFFSET C29 Power 49.56
VRESET B28 Power Supply voltage for negative reset level at micromirrors. 24.82
VRESET B3 Power 24.82
VDD C2 Power Supply voltage for LVCMOS core logic. Supply voltage for LPSDR inputs.
Supply voltage for normal high level at micromirror address electrodes.
VDD D2 Power
VDD D29 Power
VDD E2 Power
VDD E29 Power
VDD H2 Power
VDD H28 Power
VDD H29 Power
VDD J2 Power
VDD J28 Power
VDD J29 Power
VDD K2 Power
VDD K29 Power
VDD L2 Power
VDD L29 Power
VDDI E28 Power Supply voltage for SubLVDS receivers.
VDDI F2 Power
VDDI F28 Power
VDDI F29 Power
VDDI F3 Power
VDDI G2 Power
VDDI G28 Power
VDDI G29 Power
VSS B25 Ground Common return.
Ground for all power.
VSS B26 Ground
VSS B29 Ground
VSS B5 Ground
VSS C25 Ground
VSS C26 Ground
VSS C27 Ground
VSS C28 Ground
VSS C5 Ground
VSS D4 Ground
VSS D5 Ground
VSS D6 Ground
VSS E25 Ground
VSS F25 Ground
VSS F26 Ground
VSS F5 Ground
VSS F6 Ground
VSS G25 Ground
VSS G26 Ground
VSS H25 Ground
VSS H4 Ground
VSS H5 Ground
VSS H6 Ground
VSS J26 Ground
VSS J4 Ground
VSS K26 Ground
VSS K4 Ground
VSS K5 Ground
VSS K6 Ground
VSS L27 Ground
(1) Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B.
(2) Net trace lengths inside the package:
Relative dielectric constant for the FQL ceramic package is 9.8.
Propagation speed = 11.8 / sqrt (9.8) = 3.769 inches/ns.
Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm.
(3) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are also required.
Table 5-2 Test Pads
NUMBER SYSTEM BOARD
A1 Do not connect
A5 Do not connect
A6 Do not connect
A25 Do not connect
A26 Do not connect
A27 Do not connect
A28 Do not connect
A29 Do not connect
A30 Do not connect
A31 Do not connect
B30 Do not connect
B31 Do not connect
C30 Do not connect
C31 Do not connect
D1 Do not connect
E1 Do not connect