JAJSGI1B November 2018 – May 2022 DLP4710
PRODUCTION DATA
Device electrical characteristics are over Section 6.4 unless otherwise noted.
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
LPSDR | ||||||
tr | Rise slew rate(1) | (30% to 80%) × VDD, Figure 6-3 | 1 | 3 | V/ns | |
tƒ | Fall slew rate(1) | (70% to 20%) × VDD, Figure 6-3 | 1 | 3 | V/ns | |
tr | Rise slew rate(2) | (20% to 80%) × VDD, Figure 6-3 | 0.25 | V/ns | ||
tƒ | Fall slew rate(2) | (80% to 20%) × VDD, Figure 6-3 | 0.25 | V/ns | ||
tc | Cycle time LS_CLK, | Figure 6-2 | 7.7 | 8.3 | ns | |
tW(H) | Pulse duration LS_CLK high | 50% to 50% reference points, Figure 6-2 | 3.1 | ns | ||
tW(L) | Pulse duration LS_CLK low | 50% to 50% reference points, Figure 6-2 | 3.1 | ns | ||
tsu | Setup time | LS_WDATA valid before LS_CLK ↑, Figure 6-2 | 1.5 | ns | ||
th | Hold time | LS_WDATA valid after LS_CLK ↑, Figure 6-2 | 1.5 | ns | ||
tWINDOW | Window time(1)(3) | Setup time + Hold time, Figure 6-2 | 3.0 | ns | ||
tDERATING | Window time derating(1)(3) | For each 0.25 V/ns reduction in slew rate below 1 V/ns, Figure 6-5 | 0.35 | ns | ||
SubLVDS | ||||||
tr | Rise slew rate | 20% to 80% reference points, Figure 6-4 | 0.7 | 1 | V/ns | |
tƒ | Fall slew rate | 80% to 20% reference points, Figure 6-4 | 0.7 | 1 | V/ns | |
tc | Cycle time DCLK, | Figure 6-6 | 1.79 | 1.85 | ns | |
tW(H) | Pulse duration DCLK high | 50% to 50% reference points, Figure 6-6 | 0.79 | ns | ||
tW(L) | Pulse duration DCLK low | 50% to 50% reference points, Figure 6-6 | 0.79 | ns | ||
tsu | Setup time | D(0:7) valid before DCLK ↑ or DCLK ↓, Figure 6-6 |
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th | Hold time | D(0:7) valid after DCLK ↑ or DCLK ↓, Figure 6-6 |
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tWINDOW | Window time | Setup time + Hold time, Figure 6-6, Figure 6-7 | 3.0 | ns | ||
tLVDS-ENABLE+REFGEN | Power-up receiver(4) | 2000 | ns |