JAJSUJ2 May 2024
ADVANCE INFORMATION
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tpd | Output propagation, Clock to Q (C2Q), rising edge of LS_CLK (differential clock signal) input to LS_RDATA output.(1) | CL = 5pF | 11.1 | ns | ||
CL = 10pF | 11.3 | ns | ||||
Slew rate, LS_RDATA | 20%-80%, CL <10pF | 0.5 | V/ns | |||
Output duty cycle distortion, LS_RDATA_A and LS_RDATA_B | 50-(C2Q rise - C2Q fall )*130e6*100 | 40% | 60% |