JAJSUI1 May   2024 DLP472TE

ADVANCE INFORMATION  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5.     11
    6.     12
    7. 5.5  Thermal Information
    8. 5.6  Electrical Characteristics
    9. 5.7  Switching Characteristics
    10. 5.8  Timing Requirements
    11. 5.9  System Mounting Interface Loads
    12. 5.10 Micromirror Array Physical Characteristics
    13. 5.11 Micromirror Array Optical Characteristics
    14. 5.12 Window Characteristics
    15. 5.13 Chipset Component Usage Specification
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Window Aperture Illumination Overfill Calculation
    9. 6.9 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.9.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.9.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.9.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.9.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Temperature Sensor Diode
  9. Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Impedance Requirements
    3. 9.3 Layers
    4. 9.4 Trace Width, Spacing
    5. 9.5 Power
    6. 9.6 Trace Length Matching Recommendations
  11. 10Device and Documentation Support
    1. 10.1 サード・パーティ製品に関する免責事項
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 サポート・リソース
    6. 10.6 Trademarks
    7. 10.7 静電気放電に関する注意事項
    8. 10.8 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Pin Configuration and Functions

DLP472TE FYW Package149-Pin PGABottom ViewFigure 4-1 FYW Package149-Pin PGABottom View
CAUTION:

Properly manage the layout and the operation of signals identified in the Pin Functions table to make sure there is reliable, long-term operation of the 0.47” 4K UHD S453 DMD. Refer to the PCB Design Requirements for TI DLP Digital Micromirror Devices application report for specific details and guidelines before designing the board.

Table 4-1 Pin Functions
PININPUT-OUTPUT(1)DESCRIPTIONTRACE LENGTH (mm)
NAMENo.
D_AP(0)J1IHigh-speed differential data pair lane A016.24427
D_AN(0)H1IHigh-speed differential data pair lane A016.24426
D_AP(1)G1IHigh-speed differential data pair lane A116.39699
D_AN(1)F1IHigh-speed differential data pair lane A116.39691
D_AP(2)F2IHigh-speed differential data pair lane A215.58905
D_AN(2)E2IHigh-speed differential data pair lane A215.58908
D_AP(3)D2IHigh-speed differential data pair lane A314.98471
D_AN(3)C2IHigh-speed differential data pair lane A314.9844
D_AP(4)A3IHigh-speed differential data pair lane A412.89101
D_AN(4)A4IHigh-speed differential data pair lane A412.89101
D_AP(5)A5IHigh-speed differential data pair lane A510.57206
D_AN(5)A6IHigh-speed differential data pair lane A510.57242
D_AP(6)A7IHigh-speed differential data pair lane A68.48593
D_AN(6)A8IHigh-speed differential data pair lane A68.48702
D_AP(7)A9IHigh-speeddifferential data pair lane A76.63434
D_AN(7)A10IHigh-speed differential data pair lane A76.63441
DCLK_APC1IHigh-speed differential clock A15.53899
DCLK_AND1IHigh-speed differential clock A15.53868
D_BP(0)A11IHigh-speed differential data pair lane B04.52398
D_BN(0)A12IHigh-speed differential data pair lane B04.52368
D_BP(1)A13IHigh-speed differential data pair lane B16.4103
D_BN(1)A14IHigh-speed differential data pair lane B16.40894
D_BP(2)A15IHigh-speed differential data pair lane B28.78102
D_BN(2)A16IHigh-speed differential data pair lane B28.78364
D_BP(3)A18IHigh-speed differential data pair lane B312.05827
D_BN(3)A19IHigh-speed differential data pair lane B312.06154
D_BP(4)D19IHigh-speed differential data pair lane B411.04817
D_BN(4)C19IHigh-speed differential data pair lane B411.0479
D_BP(5)H20IHigh-speed differential data pair lane B514.54976
D_BN(5)J20IHigh-speed differential data pair lane B514.54991
D_BP(6)D20IHigh-speed differential data pair lane B611.67363
D_BN(6)E20IHigh-speed differential data pair lane B611.67598
D_BP(7)F20IHigh-speed differential data pair lane B712.33442
D_BN(7)G20IHigh-speed differential data pair lane B712.33409
DCLK_BPB17IHigh-speed differential clock B10.22973
DCLK_BNB18IHigh-speed differential clock B10.22551
LS_WDATA_PT10ILVDS data7.8047
LS_WDATA_NR11ILVDS data0.64391
LS_CLK_PR9ILVDS CLK8.20952
LS_CLK_NR10ILVDS CLK7.35885
LS_RDATA_A_BISTAT13OLVCMOS output2.01174
BIST_BT12OLVCMOS output2.20006
AMUX_OUTB20OAnalog test mux10.74435
DMUX_OUTR14ODigital test mux2.25459
DMD_DEN_ARSTZT11IARSTZ2.00365
TEMP_NR8ITemp diode N9.03231
TEMP_PR7ITemp diode P11.38391
VDDB13, B7, C18, E3, H3, J2, K3, L2, L19, M1, M2, N3, N19, P2, P18, R3, R5, R12, R17, R19, T2, T4, T6, T8, T18PDigital Core supply voltagePlane
VDDAB11, B16, B4, B9, C20, D3, E18, G2, G19PHSSI supply voltagePlane
VRESETB3, R1PSupply voltage for negative bias of micromirror reset signalPlane
VBIASE1, P1PSupply voltage for positive bias of micromirror reset signalPlane
VOFFSETA20, B2, T1, T20PSupply voltage for HVCMOS logic,stepped up logic levelPlane
VSSA17, B10, B14, B6, D18, F3, F19, J3, K19, K2, L1, L3, M3, N2, N18, N20, P3, P20, R2, R4, R6, R13, R20, T5, T7, T16, T17, T19GGroundPlane
VSSAB12, B15, B19, B5, B8, C3, E19, G3, H2, H19, K1, N1, P19, R18, T3, T9GGroundPlane
N/CF18, G18, H18, J18, J19, K18, K20, L18, L20, M18, M19, M20, R15, R16, T14, T15No connect
I=Input, O=Output, P=Power, G=Ground, NC = No Connect