JAJSUI1 May 2024 DLP472TE
ADVANCE INFORMATION
CAUTION: Properly manage the layout and the operation of signals identified in the Pin Functions table to make sure there is reliable, long-term operation of the 0.47” 4K UHD S453 DMD. Refer to the PCB Design Requirements for TI DLP Digital Micromirror Devices application report for specific details and guidelines before designing the board. |
PIN | INPUT-OUTPUT(1) | DESCRIPTION | TRACE LENGTH (mm) | |
---|---|---|---|---|
NAME | No. | |||
D_AP(0) | J1 | I | High-speed differential data pair lane A0 | 16.24427 |
D_AN(0) | H1 | I | High-speed differential data pair lane A0 | 16.24426 |
D_AP(1) | G1 | I | High-speed differential data pair lane A1 | 16.39699 |
D_AN(1) | F1 | I | High-speed differential data pair lane A1 | 16.39691 |
D_AP(2) | F2 | I | High-speed differential data pair lane A2 | 15.58905 |
D_AN(2) | E2 | I | High-speed differential data pair lane A2 | 15.58908 |
D_AP(3) | D2 | I | High-speed differential data pair lane A3 | 14.98471 |
D_AN(3) | C2 | I | High-speed differential data pair lane A3 | 14.9844 |
D_AP(4) | A3 | I | High-speed differential data pair lane A4 | 12.89101 |
D_AN(4) | A4 | I | High-speed differential data pair lane A4 | 12.89101 |
D_AP(5) | A5 | I | High-speed differential data pair lane A5 | 10.57206 |
D_AN(5) | A6 | I | High-speed differential data pair lane A5 | 10.57242 |
D_AP(6) | A7 | I | High-speed differential data pair lane A6 | 8.48593 |
D_AN(6) | A8 | I | High-speed differential data pair lane A6 | 8.48702 |
D_AP(7) | A9 | I | High-speeddifferential data pair lane A7 | 6.63434 |
D_AN(7) | A10 | I | High-speed differential data pair lane A7 | 6.63441 |
DCLK_AP | C1 | I | High-speed differential clock A | 15.53899 |
DCLK_AN | D1 | I | High-speed differential clock A | 15.53868 |
D_BP(0) | A11 | I | High-speed differential data pair lane B0 | 4.52398 |
D_BN(0) | A12 | I | High-speed differential data pair lane B0 | 4.52368 |
D_BP(1) | A13 | I | High-speed differential data pair lane B1 | 6.4103 |
D_BN(1) | A14 | I | High-speed differential data pair lane B1 | 6.40894 |
D_BP(2) | A15 | I | High-speed differential data pair lane B2 | 8.78102 |
D_BN(2) | A16 | I | High-speed differential data pair lane B2 | 8.78364 |
D_BP(3) | A18 | I | High-speed differential data pair lane B3 | 12.05827 |
D_BN(3) | A19 | I | High-speed differential data pair lane B3 | 12.06154 |
D_BP(4) | D19 | I | High-speed differential data pair lane B4 | 11.04817 |
D_BN(4) | C19 | I | High-speed differential data pair lane B4 | 11.0479 |
D_BP(5) | H20 | I | High-speed differential data pair lane B5 | 14.54976 |
D_BN(5) | J20 | I | High-speed differential data pair lane B5 | 14.54991 |
D_BP(6) | D20 | I | High-speed differential data pair lane B6 | 11.67363 |
D_BN(6) | E20 | I | High-speed differential data pair lane B6 | 11.67598 |
D_BP(7) | F20 | I | High-speed differential data pair lane B7 | 12.33442 |
D_BN(7) | G20 | I | High-speed differential data pair lane B7 | 12.33409 |
DCLK_BP | B17 | I | High-speed differential clock B | 10.22973 |
DCLK_BN | B18 | I | High-speed differential clock B | 10.22551 |
LS_WDATA_P | T10 | I | LVDS data | 7.8047 |
LS_WDATA_N | R11 | I | LVDS data | 0.64391 |
LS_CLK_P | R9 | I | LVDS CLK | 8.20952 |
LS_CLK_N | R10 | I | LVDS CLK | 7.35885 |
LS_RDATA_A_BISTA | T13 | O | LVCMOS output | 2.01174 |
BIST_B | T12 | O | LVCMOS output | 2.20006 |
AMUX_OUT | B20 | O | Analog test mux | 10.74435 |
DMUX_OUT | R14 | O | Digital test mux | 2.25459 |
DMD_DEN_ARSTZ | T11 | I | ARSTZ | 2.00365 |
TEMP_N | R8 | I | Temp diode N | 9.03231 |
TEMP_P | R7 | I | Temp diode P | 11.38391 |
VDD | B13, B7, C18, E3, H3, J2, K3, L2, L19, M1, M2, N3, N19, P2, P18, R3, R5, R12, R17, R19, T2, T4, T6, T8, T18 | P | Digital Core supply voltage | Plane |
VDDA | B11, B16, B4, B9, C20, D3, E18, G2, G19 | P | HSSI supply voltage | Plane |
VRESET | B3, R1 | P | Supply voltage for negative bias of micromirror reset signal | Plane |
VBIAS | E1, P1 | P | Supply voltage for positive bias of micromirror reset signal | Plane |
VOFFSET | A20, B2, T1, T20 | P | Supply voltage for HVCMOS logic,stepped up logic level | Plane |
VSS | A17, B10, B14, B6, D18, F3, F19, J3, K19, K2, L1, L3, M3, N2, N18, N20, P3, P20, R2, R4, R6, R13, R20, T5, T7, T16, T17, T19 | G | Ground | Plane |
VSSA | B12, B15, B19, B5, B8, C3, E19, G3, H2, H19, K1, N1, P19, R18, T3, T9 | G | Ground | Plane |
N/C | F18, G18, H18, J18, J19, K18, K20, L18, L20, M18, M19, M20, R15, R16, T14, T15 | No connect |