JAJSUI1 May   2024 DLP472TE

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5.     11
    6.     12
    7. 5.5  Thermal Information
    8. 5.6  Electrical Characteristics
    9. 5.7  Switching Characteristics
    10. 5.8  Timing Requirements
    11. 5.9  System Mounting Interface Loads
    12. 5.10 Micromirror Array Physical Characteristics
    13. 5.11 Micromirror Array Optical Characteristics
    14. 5.12 Window Characteristics
    15. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Window Aperture Illumination Overfill Calculation
    9. 6.9 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.9.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.9.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.9.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.9.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Temperature Sensor Diode
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Impedance Requirements
    3. 9.3 Layers
    4. 9.4 Trace Width, Spacing
    5. 9.5 Power
    6. 9.6 Trace Length Matching Recommendations
  11. 10Device and Documentation Support
    1. 10.1 サード・パーティ製品に関する免責事項
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 サポート・リソース
    6. 10.6 Trademarks
    7. 10.7 静電気放電に関する注意事項
    8. 10.8 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2 DMD Power Supply Power-Down Procedure

  • During power-down, VDD must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within the specified limit of ground. See Table 8-1.
  • During power-down, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be within the specified limit shown in the recommended operating conditions.
  • During power-down, there is no requirement for the relative timing of VRESET with respect to VBIAS.
  • Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the requirements specified in the absolute maximum ratings, in the recommended operating conditions, and in Table 8-1.
  • During power-down, LVCMOS input pins must be less than specified in the recommended operating conditions.
DLP472TE DMD Power Supply Requirements
A. See Table 4-1 for pin functions.
B. To prevent excess current, the supply voltage difference |VBIAS – VOFFSET| must be less than the specified limit in the recommended operating conditions.
C. To prevent excess current, the supply difference |VBIAS – VRESET| must be less than the specified limit in the recommended operating conditions.
D. VBIAS must power up after VOFFSET has powered up, per the tDELAY1 specification in Table 8-1.
E. VRESET, VOFFSET, VBIAS ramps must start after VDD and BDDA are powered up and stable.
F. After the DMD micromirror park sequence is complete, the DLP controller software initiates a hardware power-down that activates DMD_EN_ARSTZ and disables VBIAS, VRESET and VOFFSET.
G. Under power-loss conditions where emergency DMD micromirror park procedures are being enacted by the DLP controller hardware DMD_EN_ARSTZ goes low.
H. VDD must remain high until after VOFFSET, VBIAS, VRESET go low, per Delay2 specification in the Table 8-1.
I. To prevent excess current, the supply voltage delta |VDDA – VDD| must be less than specified limit in the recommended operating conditions.
J. Not to scale. Details omitted for clarity.
Figure 8-1 DMD Power Supply Requirements