JAJSQF9
August 2024
DLP472TP
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
4.1
Pin Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
Storage Conditions
5.3
ESD Ratings
5.4
Recommended Operating Conditions
12
5.5
Thermal Information
5.6
Electrical Characteristics
5.7
Switching Characteristics
5.8
Timing Requirements
17
5.9
System Mounting Interface Loads
19
5.10
Micromirror Array Physical Characteristics
21
5.11
Micromirror Array Optical Characteristics
23
5.12
Window Characteristics
5.13
Chipset Component Usage Specification
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Power Interface
6.3.2
LPSDR Low-Speed Interface
6.3.3
High-Speed Interface
6.3.4
Timing
6.4
Device Functional Modes
6.5
Optical Interface and System Image Quality Considerations
6.5.1
Numerical Aperture and Stray Light Control
6.5.2
Pupil Match
6.5.3
Illumination Overfill
6.6
Micromirror Array Temperature Calculation
6.7
Micromirror Power Density Calculation
6.8
Micromirror Landed-On/Landed-Off Duty Cycle
6.8.1
Definition of Micromirror Landed-On/Landed-Off Duty Cycle
6.8.2
Landed Duty Cycle and Useful Life of the DMD
6.8.3
Landed Duty Cycle and Operational DMD Temperature
6.8.4
Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
7
Application and Implementation
7.1
Application Information
7.2
Typical Application
7.2.1
Design Requirements
7.2.2
Detailed Design Procedure
7.2.3
Application Curve
7.3
Temperature Sensor Diode
8
Power Supply Recommendations
8.1
DMD Power Supply Power-Up Procedure
8.2
DMD Power Supply Power-Down Procedure
9
Layout
9.1
Layout Guidelines
9.2
Layout Example
10
Device and Documentation Support
10.1
サード・パーティ製品に関する免責事項
10.2
Device Support
10.2.1
Device Nomenclature
10.2.2
Device Markings
10.3
Documentation Support
10.3.1
Related Documentation
10.4
ドキュメントの更新通知を受け取る方法
10.5
Trademarks
10.6
静電気放電に関する注意事項
10.7
用語集
11
Revision History
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
FQY|174
MCLG050
サーマルパッド・メカニカル・データ
発注情報
jajsqf9_oa
The low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B,
Low Power Double Data Rate (LPDDR)
JESD209B
.
Figure 5-2
LPSDR Switching Parameters
Figure 5-3
LPSDR Input Rise and Fall Slew Rate
Figure 5-4
SubLVDS Input Rise and Fall Slew Rate
Figure 5-5
Window Time Derating Concept
Figure 5-6
SubLVDS Switching Parameters
Note: Refer to
Section 5.8
for details.
Figure 5-7
High-Speed Training Scan Window
Figure 5-8
SubLVDS Voltage Parameters
Figure 5-9
SubLVDS Waveform Parameters
Figure 5-10
SubLVDS Equivalent Input Circuit
Figure 5-11
LPSDR Input Hysteresis
Figure 5-12
LPSDR Read Out
See
Section 5.6
for more information.
Figure 5-13
Test Load Circuit for Output Propagation Measurement