JAJSGT9G April   2010  – January 2019 DLP5500

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Storage Conditions
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  Timing Requirements
    8. 7.8  System Mounting Interface Loads
    9. 7.9  Micromirror Array Physical Characteristics
    10. 7.10 Micromirror Array Optical Characteristics
    11. 7.11 Window Characteristics
    12. 7.12 Chipset Component Usage Specification
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Video Modes
      2. 8.4.2 Structured Light Modes
        1. 8.4.2.1 Static Image Buffer Mode
        2. 8.4.2.2 Real Time Structured Light Mode
    5. 8.5 Window Characteristics and Optics
      1. 8.5.1 Optical Interface and System Image Quality
      2. 8.5.2 Numerical Aperture and Stray Light Control
      3. 8.5.3 Pupil Match
      4. 8.5.4 Illumination Overfill
    6. 8.6 Micromirror Array Temperature Calculation
      1. 8.6.1 Package Thermal Resistance
      2. 8.6.2 Case Temperature
      3. 8.6.3 Micromirror Array Temperature Calculation for Uniform Illumination
    7. 8.7 Micromirror Landed-on/Landed-Off Duty Cycle
      1. 8.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 8.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 8.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 8.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 DLP5500 System Interface
  10. 10Power Supply Recommendations
    1. 10.1 DMD Power-Up and Power-Down Procedures
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Impedance Requirements
      2. 11.1.2 PCB Signal Routing
      3. 11.1.3 Fiducials
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイスの項目表記
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連資料
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • FYA|149
サーマルパッド・メカニカル・データ
発注情報

7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
SUPPLY VOLTAGES(1)(2)
VCC Supply voltage for LVCMOS core logic 3.15 3.3 3.45 V
VCCI Supply voltage for LVDS receivers 3.15 3.3 3.45 V
VCC2 Mirror electrode and HVCMOS supply voltage 8.25 8.5 8.75 V
|VCCI–VCC| Supply voltage delta (absolute value) (3) 0.3 V
VMBRST Micromirror clocking pulse voltages -27 26.5 V
LVCMOS PINS
VIH High level Input voltage (4) 1.7 2.5 VCC + 0.15 V
VIL Low level Input voltage(4) – 0.3 0.7 V
IOH High level output current at VOH = 2.4 V –20 mA
IOL Low level output current at VOL = 0.4 V 15 mA
TPWRDNZ PWRDNZ pulse width(5) 10 ns
SCP INTERFACE
ƒclock SCP clock frequency(6) 500 kHz
tSCP_SKEW Time between valid SCPDI and rising edge of SCPCLK(7) –800 800 ns
tSCP_DELAY Time between valid SCPDO and rising edge of SCPCLK(7) 700 ns
tSCP_BYTE_INTERVAL Time between consecutive bytes 1 µs
tSCP_NEG_ENZ Time between falling edge of SCPENZ and the first rising edge of SCPCLK 30 ns
tSCP_PW_ENZ SCPENZ inactive pulse width (high level) 1 µs
tSCP_OUT_EN Time required for SCP output buffer to recover after SCPENZ (from tri-state) 1.5 ns
ƒclock SCP circuit clock oscillator frequency (8) 9.6 11.1 MHz
LVDS INTERFACE
ƒclock Clock frequency for LVDS interface, DCLK (all channels) 200 MHz
|VID| Input differential voltage (absolute value)(9) 100 400 600 mV
VCM Common mode (9) 1200 mV
VLVDS LVDS voltage(9) 0 2000 mV
tLVDS_RSTZ Time required for LVDS receivers to recover from PWRDNZ 10 ns
ZIN Internal differential termination resistance 95 105 Ω
ZLINE Line differential impedance (PWB/trace) 90 100 110 Ω
ENVIRONMENTAL (10)
TDMD Long-term DMD temperature (operational) (11)(12)(16) 10 40 to 70(12) °C
Short-term DMD temperature (operational)(11)(17) –20 75 °C
TWINDOW Window temperature – operational(13) 90 °C
TCERAMIC-WINDOW-DELTA Delta ceramic-to-window temperature -operational (13)(14) 30 °C
Long-term dew point (operational & non-operational) 24 °C
Short-term dew point(16)(18) (operational & non-operational) 28 °C
ILLUV Illumination, wavelength < 420 nm 0.68 mW/cm2
ILLVIS Illumination, wavelengths between 420 and 700 nm Thermally Limited(15) mW/cm2
ILLIR Illumination, wavelength > 700 nm 10 mW/cm2
(1) Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.
(2) VOFFSET supply transients must fall within specified max voltages.
(3) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.
(4) Tester Conditions for VIH and VIL:
Frequency = 60MHz. Maximum Rise Time = 2.5 ns at (20% to 80%)
Frequency = 60MHz. Maximum Fall Time = 2.5 ns at (80% to 20%)
(5) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tri-states the SCPDO output pin.
(6) The SCP clock is a gated clock. Duty cycle shall be 50% ± 10%. SCP parameter is related to the frequency of DCLK.
(7) Refer to Figure 3.
(8) SCP internal oscillator is specified to operate all SCP registers. For all SCP operations, DCLK is required.
(9) Refer to Figure 5, Figure 6, and Figure 7.
(10) Optimal, long-term performance and optical efficiency of the Digital Micromirror Device (DMD) can be affected by various application parameters, including illumination spectrum, illumination power density, micromirror landed duty-cycle, ambient temperature (storage and operating), DMD temperature, ambient humidity (storage and operating), and power on or off duty cycle. TI recommends that application-specific effects be considered as early as possible in the design cycle.
(11) DMD Temperature is the worst-case of any thermal test point in Figure 16, or the active array as calculated by the Micromirror Array Temperature Calculation for Uniform Illumination.
(12) Per Figure 1, the maximum operational case temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Micromirror Landed-on/Landed-Off Duty Cycle for a definition of micromirror landed duty cycle.
(13) Window temperature as measured at thermal test points TP2, TP3, TP4 and TP5 in Figure 16.The locations of thermal test points TP2, TP3, TP4 and TP5 in Figure 16 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, a test point should be added to that location.
(14) Ceramic package temperature as measured at test point 1 (TP 1) in Figure 16.
(16) Long-term is defined as the average over the usable life of the device.
(17) Short-term is defined as less than 60 cumulative days over the over the usable life of the device.
(18) Dew points beyond the specified long-term dew point (operating, non-operating, or storage) are for short-term conditions only, where short-term is defined as< 60 cumulative days over the usable life of the device.
DLP5500 derating_curve_LPS046_update.gifFigure 1. Max Recommended DMD Temperature – Derating Curve