JAJSGT9G April   2010  – January 2019 DLP5500

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Storage Conditions
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  Timing Requirements
    8. 7.8  System Mounting Interface Loads
    9. 7.9  Micromirror Array Physical Characteristics
    10. 7.10 Micromirror Array Optical Characteristics
    11. 7.11 Window Characteristics
    12. 7.12 Chipset Component Usage Specification
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Video Modes
      2. 8.4.2 Structured Light Modes
        1. 8.4.2.1 Static Image Buffer Mode
        2. 8.4.2.2 Real Time Structured Light Mode
    5. 8.5 Window Characteristics and Optics
      1. 8.5.1 Optical Interface and System Image Quality
      2. 8.5.2 Numerical Aperture and Stray Light Control
      3. 8.5.3 Pupil Match
      4. 8.5.4 Illumination Overfill
    6. 8.6 Micromirror Array Temperature Calculation
      1. 8.6.1 Package Thermal Resistance
      2. 8.6.2 Case Temperature
      3. 8.6.3 Micromirror Array Temperature Calculation for Uniform Illumination
    7. 8.7 Micromirror Landed-on/Landed-Off Duty Cycle
      1. 8.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 8.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 8.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 8.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 DLP5500 System Interface
  10. 10Power Supply Recommendations
    1. 10.1 DMD Power-Up and Power-Down Procedures
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Impedance Requirements
      2. 11.1.2 PCB Signal Routing
      3. 11.1.3 Fiducials
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイスの項目表記
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連資料
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • FYA|149
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

FYA Package
149-Pin CPGA Series 450
Bottom View
DLP5500 po_lps013.gif

Pin Functions

PIN(1) TYPE
(I/O/P )		 SIGNAL DATA
RATE(2) 		INTERNAL
TERM(3) 		CLOCK DESCRIPTION TRACE
(mils)(4)
NAME NO.
DATA INPUTS
D_AN1 G20 Input LVCMOS DDR Differential DCLK_A Input data bus A (LVDS) 715
D_AP1 H20 Input LVCMOS DDR Differential DCLK_A 744
D_AN3 H19 Input LVCMOS DDR Differential DCLK_A 688
D_AP3 G19 Input LVCMOS DDR Differential DCLK_A 703
D_AN5 F18 Input LVCMOS DDR Differential DCLK_A 686
D_AP5 G18 Input LVCMOS DDR Differential DCLK_A 714
D_AN7 E18 Input LVCMOS DDR Differential DCLK_A 689
D_AP7 D18 Input LVCMOS DDR Differential DCLK_A 705
D_AN9 C20 Input LVCMOS DDR Differential DCLK_A 687
D_AP9 D20 Input LVCMOS DDR Differential DCLK_A 715
D_AN11 B18 Input LVCMOS DDR Differential DCLK_A 715
D_AP11 A18 Input LVCMOS DDR Differential DCLK_A 732
D_AN13 A20 Input LVCMOS DDR Differential DCLK_A 686
D_AP13 B20 Input LVCMOS DDR Differential DCLK_A 715
D_AN15 B19 Input LVCMOS DDR Differential DCLK_A 700
D_AP15 A19 Input LVCMOS DDR Differential DCLK_A 719
D_BN1 K20 Input LVCMOS DDR Differential DCLK_B Input data bus B (LVDS) 716
D_BP1 J20 Input LVCMOS DDR Differential DCLK_B 745
D_BN3 J19 Input LVCMOS DDR Differential DCLK_B 686
D_BP3 K19 Input LVCMOS DDR Differential DCLK_B 703
D_BN5 L18 Input LVCMOS DDR Differential DCLK_B 686
D_BP5 K18 Input LVCMOS DDR Differential DCLK_B 714
D_BN7 M18 Input LVCMOS DDR Differential DCLK_B 693
D_BP7 N18 Input LVCMOS DDR Differential DCLK_B 709
D_BN9 P20 Input LVCMOS DDR Differential DCLK_B 687
D_BP9 N20 Input LVCMOS DDR Differential DCLK_B 715
D_BN11 R18 Input LVCMOS DDR Differential DCLK_B 702
D_BP11 T18 Input LVCMOS DDR Differential DCLK_B 719
D_BN13 T20 Input LVCMOS DDR Differential DCLK_B 686
D_BP13 R20 Input LVCMOS DDR Differential DCLK_B 715
D_BN15 R19 Input LVCMOS DDR Differential DCLK_B 680
D_BP15 T19 Input LVCMOS DDR Differential DCLK_B 700
DCLK_AN D19 Input LVCMOS - Differential – Input data bus A Clock (LVDS) 700
DCLK_AP E19 Input LVCMOS - Differential – 728
DCLK_BN N19 Input LVCMOS - Differential – Input data bus B Clock (LVDS) 700
DCLK_BP M19 Input LVCMOS - Differential – 728
DATA CONTROL INPUTS
SCTRL_AN F20 Input LVCMOS DDR Differential DCLK_A Data Control (LVDS) 716
SCTRL_AP E20 Input LVCMOS DDR Differential DCLK_A 731
SCTRL_BN L20 Input LVCMOS DDR Differential DCLK_B 707
SCTRL_BP M20 Input LVCMOS DDR Differential DCLK_B 722
SERIAL COMMUNICATION (SCP) AND CONFIGURATION
SCP_CLK A8 Input LVCMOS – Pull-Down – –
SCP_DO A9 Output LVCMOS – – SCP_CLK –
SCP_DI A5 Input LVCMOS – Pull-Down SCP_CLK –
SCP_EN B7 Input LVCMOS – Pull-Down SCP_CLK –
PWRDN B9 Input LVCMOS – Pull-Down – –
MICROMIRROR BIAS CLOCKING PULSE
MODE_A A4 Input LVCMOS – Pull-Down – –
MBRST0 C3 Input Analog – – – Micromirror Bias Clocking Pulse "MBRST" signals "clock" micromirrors into state of LVCMOS memory cell associated with each mirror. –
MBRST1 D2 Input Analog – – – –
MBRST2 D3 Input Analog – – – –
MBRST3 E2 Input Analog – – – –
MBRST4 G3 Input Analog – – – –
MBRST5 E1 Input Analog – – – –
MBRST6 G2 Input Analog – – – –
MBRST7 G1 Input Analog – – – –
MBRST8 N3 Input Analog – – – –
MBRST9 M2 Input Analog – – – –
MBRST10 M3 Input Analog – – – –
MBRST11 L2 Input Analog – – – –
MBRST12 J3 Input Analog – – – –
MBRST13 L1 Input Analog – – – –
MBRST14 J2 Input Analog – – – –
MBRST15 J1 Input Analog – – – –
POWER
VCC B11,B12,B13,B16,R12,R13,R16,R17 Power Analog – – – Power for LVCMOS Logic –
VCCI A12,A14,A16,T12,T14,T16 Power Analog – – – Power supply for LVDS Interface –
VCC2 C1,D1,M1,N1 Power Analog – – – Power for High Voltage CMOS Logic –
VSS A6,A11,A13,A15,A17,B4,B5,B8,B14,B15,B17,C2,C18,C19,F1,F2,F19,H1,H2,H3,H18,J18,K1,K2,L19,N2,P18,P19,R4,R9,R14,R15,T7,T13,T15,T17 Power Analog – – – Common return for all power inputs –
RESERVED SIGNALS (Not for use in system)
RESERVED_R7 R7 Input LVCMOS – Pull-Down – Pins should be connected to VSS –
RESERVED_R8 R8 Input LVCMOS – Pull-Down – –
RESERVED_T8 T8 Input LVCMOS – Pull-Down – –
RESERVED_B6 B6 Input LVCMOS – Pull-Down – –
NO_CONNECT A3, A7, A10, B2, B3, B10, E3, F3, K3, L3, P1, P2, P3, R1, R2, R3, R5, R6, R10, R11, T1, T2, T3, T4, T5, T6, T9, T10, T11 – – – – – DO NOT CONNECT –
(1) The following power supplies are required to operate the DMD: VCC, VCCI, VCC2. VSS must also be connected.
(2) DDR = Double Data Rate. SDR = Single Data Rate. Refer to the Timing Requirements for specifications and relationships.
(3) Refer to Electrical Characteristics for differential termination specification.
(4) Internal Trace Length (mils) refers to the Package electrical trace length. See the DLP® 0.55 XGA Chip-Set Data Manual (DLPZ004) for details regarding signal integrity considerations for end-equipment designs.