JAJSHY3 データシート

JAJSHY3 September 2019 DLP5534-Q1

ADVANCE INFORMATION for pre-production products; subject to change without notice.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

FYK|149
- MCPS005A

サーマルパッド・メカニカル・データ

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6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS⁽²⁾	MIN	TYP⁽¹⁰⁾	MAX	UNIT
CURRENT
I_DD	Supply current: VDD⁽³⁾⁽⁴⁾	VDD = 1.95 V			369	mA
I_DD	Supply current: VDD⁽³⁾⁽⁴⁾	VDD = 1.8 V				mA
I_DDI	Supply current: VDDI⁽³⁾⁽⁴⁾	VDDI = 1.95 V			62	mA
I_DDI	Supply current: VDDI⁽³⁾⁽⁴⁾	VDD = 1.8 V				mA
I_OFFSET	Supply current: VOFFSET⁽⁵⁾	VOFFSET = 8.75 V			16.1	mA
I_OFFSET	Supply current: VOFFSET⁽⁵⁾	VOFFSET = 8.5 V				mA
I_BIAS	Supply current: VBIAS⁽⁵⁾	VBIAS = 16.5 V			1.3	mA
I_BIAS	Supply current: VBIAS⁽⁵⁾	VBIAS = 16 V				mA
I_RESET	Supply current: VRESET	VRESET = –10.5 V			–10.2	mA
I_RESET	Supply current: VRESET	VRESET = –10 V				mA
POWER⁽⁹⁾
P_DD	Supply power dissipation: VDD⁽³⁾⁽⁴⁾	VDD = 1.95 V			720	mW
P_DD	Supply power dissipation: VDD⁽³⁾⁽⁴⁾	VDD = 1.8 V				mW
P_DDI	Supply power dissipation: VDDI⁽³⁾⁽⁴⁾	VDDI = 1.95 V			121	mW
P_DDI	Supply power dissipation: VDDI⁽³⁾⁽⁴⁾	VDD = 1.8 V				mW
P_OFFSET	Supply power dissipation: VOFFSET⁽⁵⁾	VOFFSET = 8.75 V			141	mW
P_OFFSET	Supply power dissipation: VOFFSET⁽⁵⁾	VOFFSET = 8.5 V				mW
P_BIAS	Supply power dissipation: VBIAS⁽⁵⁾	VBIAS = 16.5 V			22	mW
P_BIAS	Supply power dissipation: VBIAS⁽⁵⁾	VBIAS = 16 V				mW
P_RESET	Supply power dissipation: VRESET	VRESET = –10.5 V			108	mW
P_RESET	Supply power dissipation: VRESET	VRESET = –10 V				mW
P_TOTAL	Supply power dissipation: Total				1110	mW
LPSDR INPUT⁽⁶⁾
V_IH(DC)	DC input high voltage⁽⁷⁾		0.7 × VDD		VDD + 0.3	V
V_IL(DC)	DC input low voltage⁽⁷⁾		–0.3		0.3 × VDD	V
V_IH(AC)	AC input high voltage⁽⁷⁾		0.8 × VDD		VDD + 0.3	V
V_IL(AC)	AC input low voltage		–0.3		0.2 × VDD	V
∆V_T	Hysteresis (V_T+ – V_T–)	See Figure 9	0.1 × VDD		0.4 × VDD	V
I_IL	Low–level input current	VDD = 1.95 V; V_I = 0 V	–100			nA
I_IH	High–level input current	VDD = 1.95 V; V_I = 1.95 V			300	nA
LPSDR OUTPUT⁽⁸⁾
V_OH	DC output high voltage	I_OH = –2 mA	0.8 × VDD			V
V_OL	DC output low voltage	I_OL = 2 mA			0.2 × VDD	V
CAPACITANCE
C_IN	Input capacitance LPSDR	ƒ = 1 MHz			10	pF
C_IN	Input capacitance SubLVDS	ƒ = 1 MHz			20	pF
C_OUT	Output capacitance	ƒ = 1 MHz			10	pF
C_RESET	Reset group capacitance	ƒ = 1 MHz; (1152 × 144) micromirrors	350	400	450	pF
C_TEMP	Temperature sense diode capacitance	ƒ = 1 MHz			20	pF

(1) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

(2) All voltage values are with respect to the ground pins (VSS).

(3) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than the specified limit.

(4) Supply power dissipation based on non–compressed commands and data.

(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit.

(6) LPSDR input specifications are for pin DMD_DEN_ARSTZ.

(7) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.

(8) LPSDR output specification is for pins LS_RDATA_A and LS_RDATA_B.

(9) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are also required.

(10) Typical current consumption is application and video content dependent. Please see a TI applications engineer for additional information.