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Featuring over 2 million micromirrors, the high resolution 0.65 1080p digital micromirror device (DMD) is a spatial light modulator (SLM) that modulates the amplitude, direction, and/or phase of incoming light. The unique capability offered by the DLP6500 makes it well suited to support a wide variety of industrial, medical, and advanced imaging applications. Reliable function and operation of the DLP6500 requires that it be used in conjunction with the DLPC900 or the DLPC910 digital controllers. This dedicated chipset provides full HD resolution at high speeds and can be easily integrated into a variety of end equipment solutions.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DLP6500 | FYE (350) | 35.0 mm × 32.2 mm × 5.1 mm |
Changes from A Revision (February 2016) to B Revision
Changes from * Revision (October 2014) to A Revision
PIN(1) | TYPE (I/O/P) |
SIGNAL | DATA RATE(2) |
INTERNAL TERM(3) |
DESCRIPTION | TRACE (mils)(4) |
|
---|---|---|---|---|---|---|---|
NAME | NO. | ||||||
DATA BUS A | |||||||
D_AN(0) | B14 | Input | LVDS | DDR | Differential | Data, Negative | 494.88 |
D_AN(1) | B15 | Input | LVDS | DDR | Differential | Data, Negative | 486.18 |
D_AN(2) | C16 | Input | LVDS | DDR | Differential | Data, Negative | 495.16 |
D_AN(3) | K24 | Input | LVDS | DDR | Differential | Data, Negative | 485.67 |
D_AN(4) | B18 | Input | LVDS | DDR | Differential | Data, Negative | 494.76 |
D_AN(5) | L24 | Input | LVDS | DDR | Differential | Data, Negative | 490.63 |
D_AN(6) | C19 | Input | LVDS | DDR | Differential | Data, Negative | 495.16 |
D_AN(7) | H24 | Input | LVDS | DDR | Differential | Data, Negative | 485.55 |
D_AN(8) | H23 | Input | LVDS | DDR | Differential | Data, Negative | 495.16 |
D_AN(9) | B25 | Input | LVDS | DDR | Differential | Data, Negative | 485.59 |
D_AN(10) | D24 | Input | LVDS | DDR | Differential | Data, Negative | 495.16 |
D_AN(11) | E25 | Input | LVDS | DDR | Differential | Data, Negative | 495.16 |
D_AN(12) | F25 | Input | LVDS | DDR | Differential | Data, Negative | 490.04 |
D_AN(13) | H25 | Input | LVDS | DDR | Differential | Data, Negative | 485.91 |
D_AN(14) | L25 | Input | LVDS | DDR | Differential | Data, Negative | 495.16 |
D_AN(15) | G24 | Input | LVDS | DDR | Differential | Data, Negative | 495.16 |
D_AP(0) | C14 | Input | LVDS | DDR | Differential | Data, Positive | 494.84 |
D_AP(1) | B16 | Input | LVDS | DDR | Differential | Data, Positive | 486.22 |
D_AP(2) | C17 | Input | LVDS | DDR | Differential | Data, Positive | 494.65 |
D_AP(3) | K23 | Input | LVDS | DDR | Differential | Data, Positive | 488.42 |
D_AP(4) | B19 | Input | LVDS | DDR | Differential | Data, Positive | 495.16 |
D_AP(5) | L23 | Input | LVDS | DDR | Differential | Data, Positive | 490.67 |
D_AP(6) | C20 | Input | LVDS | DDR | Differential | Data, Positive | 498.11 |
D_AP(7) | J24 | Input | LVDS | DDR | Differential | Data, Positive | 486.22 |
D_AP(8) | J23 | Input | LVDS | DDR | Differential | Data, Positive | 495.47 |
D_AP(9) | C25 | Input | LVDS | DDR | Differential | Data, Positive | 485.94 |
D_AP(10) | E24 | Input | LVDS | DDR | Differential | Data, Positive | 495.16 |
D_AP(11) | D25 | Input | LVDS | DDR | Differential | Data, Positive | 494.13 |
D_AP(12) | G25 | Input | LVDS | DDR | Differential | Data, Positive | 488.98 |
D_AP(13) | J25 | Input | LVDS | DDR | Differential | Data, Positive | 492.56 |
D_AP(14) | K25 | Input | LVDS | DDR | Differential | Data, Positive | 495.16 |
D_AP(15) | F24 | Input | LVDS | DDR | Differential | Data, Positive | 495.16 |
DATA BUS B | |||||||
D_BN(0) | Z14 | Input | LVDS | DDR | Differential | Data, Negative | 494.92 |
D_BN(1) | Z15 | Input | LVDS | DDR | Differential | Data, Negative | 486.18 |
D_BN(2) | Y16 | Input | LVDS | DDR | Differential | Data, Negative | 496.46 |
D_BN(3) | P24 | Input | LVDS | DDR | Differential | Data, Negative | 493.74 |
D_BN(4) | Z18 | Input | LVDS | DDR | Differential | Data, Negative | 494.76 |
D_BN(5) | N24 | Input | LVDS | DDR | Differential | Data, Negative | 495.16 |
D_BN(6) | Y19 | Input | LVDS | DDR | Differential | Data, Negative | 492.16 |
D_BN(7) | T24 | Input | LVDS | DDR | Differential | Data, Negative | 492.68 |
D_BN(8) | T23 | Input | LVDS | DDR | Differential | Data, Negative | 484.45 |
D_BN(9) | Z25 | Input | LVDS | DDR | Differential | Data, Negative | 492.09 |
D_BN(10) | X24 | Input | LVDS | DDR | Differential | Data, Negative | 497.72 |
D_BN(11) | W25 | Input | LVDS | DDR | Differential | Data, Negative | 495.16 |
D_BN(12) | V25 | Input | LVDS | DDR | Differential | Data, Negative | 484.17 |
D_BN(13) | T25 | Input | LVDS | DDR | Differential | Data, Negative | 481.42 |
D_BN(14) | N25 | Input | LVDS | DDR | Differential | Data, Negative | 495.16 |
D_BN(15) | U24 | Input | LVDS | DDR | Differential | Data, Negative | 489.8 |
D_BP(0) | Y14 | Input | LVDS | DDR | Differential | Data, Positive | 494.88 |
D_BP(1) | Z16 | Input | LVDS | DDR | Differential | Data, Positive | 486.26 |
D_BP(2) | Y17 | Input | LVDS | DDR | Differential | Data, Positive | 495.16 |
D_BP(3) | P23 | Input | LVDS | DDR | Differential | Data, Positive | 492.48 |
D_BP(4) | Z19 | Input | LVDS | DDR | Differential | Data, Positive | 495.16 |
D_BP(5) | N23 | Input | LVDS | DDR | Differential | Data, Positive | 497.99 |
D_BP(6) | Y20 | Input | LVDS | DDR | Differential | Data, Positive | 495.16 |
D_BP(7) | R24 | Input | LVDS | DDR | Differential | Data, Positive | 492.05 |
D_BP(8) | R23 | Input | LVDS | DDR | Differential | Data, Positive | 484.45 |
D_BP(9) | Y25 | Input | LVDS | DDR | Differential | Data, Positive | 492.24 |
D_BP(10) | W24 | Input | LVDS | DDR | Differential | Data, Positive | 495.16 |
D_BP(11) | X25 | Input | LVDS | DDR | Differential | Data, Positive | 494.72 |
D_BP(12) | U25 | Input | LVDS | DDR | Differential | Data, Positive | 483.78 |
D_BP(13) | R25 | Input | LVDS | DDR | Differential | Data, Positive | 489.13 |
D_BP(14) | P25 | Input | LVDS | DDR | Differential | Data, Positive | 499.53 |
D_BP(15) | V24 | Input | LVDS | DDR | Differential | Data, Positive | 488.66 |
SERIAL CONTROL | |||||||
SCTRL_AN | C23 | Input | LVDS | DDR | Differential | Serial Control, Negative | 492.95 |
SCTRL_BN | Y23 | Input | LVDS | DDR | Differential | Serial Control, Negative | 493.78 |
SCTRL_AP | C24 | Input | LVDS | DDR | Differential | Serial Control, Positive | 493.78 |
SCTRL_BP | Y24 | Input | LVDS | DDR | Differential | Serial Control, Positive | 493.11 |
CLOCKS | |||||||
DCLK_AN | B23 | Input | LVDS | Differential | Clock, Negative | 480.35 | |
DCLK_BN | Z23 | Input | LVDS | Differential | Clock, Negative | 486.22 | |
DCLK_AP | B22 | Input | LVDS | Differential | Clock, Positive | 485.83 | |
DCLK_BP | Z22 | Input | LVDS | Differential | Clock, Positive | 491.93 | |
SERIAL COMMUNICATIONS PORT (SCP) | |||||||
SCP_DO | B8 | Output | LVCMOS | SDR | Serial Communications Port Output | ||
SCP_DI | B7 | Input | LVCMOS | SDR | Pull-Down | Serial Communications Port Data Input | |
SCP_CLK | B6 | Input | LVCMOS | Pull-Down | Serial Communications Port Clock | ||
SCP_ENZ | C8 | Input | LVCMOS | Pull-Down | Active-low Serial Communications Port Enable | ||
MICROMIRROR RESET CONTROL | |||||||
RESET_ADDR(0) | X9 | Input | LVCMOS | Pull-Down | Reset Driver Address Select | ||
RESET_ADDR(1) | X8 | Input | LVCMOS | Pull-Down | Reset Driver Address Select | ||
RESET_ADDR(2) | Z8 | Input | LVCMOS | Pull-Down | Reset Driver Address Select | ||
RESET_ADDR(3) | Z7 | Input | LVCMOS | Pull-Down | Reset Driver Address Select | ||
RESET_MODE(0) | W11 | Input | LVCMOS | Pull-Down | Reset Driver Mode Select | ||
RESET_MODE(1) | Z10 | Input | LVCMOS | Pull-Down | Reset Driver Mode Select | ||
RESET_SEL(0) | Y10 | Input | LVCMOS | Pull-Down | Reset Driver Level Select | ||
RESET_SEL(1) | Y9 | Input | LVCMOS | Pull-Down | Reset Driver Level Select | ||
RESET_STROBE | Y7 | Input | LVCMOS | Pull-Down | Reset Address, Mode, & Level latched on rising-edge | ||
ENABLES & INTERRUPTS | |||||||
PWRDNZ | D2 | Input | LVCMOS | Pull-Down | Active-low Device Reset | ||
RESET_OEZ | W7 | Input | LVCMOS | Pull-Down | Active-low output enable for DMD reset driver circuits | ||
RESETZ | Z6 | Input | LVCMOS | Pull-Down | Active-low sets Reset circuits in known VOFFSET state | ||
RESET_IRQZ | Z5 | Output | LVCMOS | Active-low, output interrupt to ASIC | |||
VOLTAGE REGULATOR MONITORING | |||||||
PG_BIAS | E11 | Input | LVCMOS | Pull-Up | Active-low fault from external VBIAS regulator | ||
PG_OFFSET | B10 | Input | LVCMOS | Pull-Up | Active-low fault from external VOFFSET regulator | ||
PG_RESET | D11 | Input | LVCMOS | Pull-Up | Active-low fault from external VRESET regulator | ||
EN_BIAS | D9 | Output | LVCMOS | Active-high enable for external VBIAS regulator | |||
EN_OFFSET | C9 | Output | LVCMOS | Active-high enable for external VOFFSET regulator | |||
EN_RESET | E9 | Output | LVCMOS | Active-high enable for external VRESET regulator | |||
LEAVE PIN UNCONNECTED | |||||||
MBRST(0) | C2 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(1) | C3 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(2) | C5 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(3) | C4 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(4) | E5 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(5) | E4 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(6) | E3 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(7) | G4 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(8) | G3 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(9) | G2 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(10) | J4 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(11) | J3 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(12) | J2 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(13) | L4 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(14) | L3 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(15) | L2 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
LEAVE PIN UNCONNECTED | |||||||
RESERVED_PFE | E7 | Input | LVCMOS | Pull-Down | For proper DMD operation, do not connect | ||
RESERVED_TM | D13 | Input | LVCMOS | Pull-Down | For proper DMD operation, do not connect | ||
RESERVED_XI1 | E13 | Input | LVCMOS | Pull-Down | For proper DMD operation, do not connect | ||
RESERVED_TP0 | W12 | Input | Analog | For proper DMD operation, do not connect | |||
RESERVED_TP1 | Y11 | Input | Analog | For proper DMD operation, do not connect | |||
RESERVED_TP2 | X11 | Input | Analog | For proper DMD operation, do not connect | |||
LEAVE PIN UNCONNECTED | |||||||
RESERVED_BA | Y12 | Output | LVCMOS | For proper DMD operation, do not connect | |||
RESERVED_BB | C12 | Output | LVCMOS | For proper DMD operation, do not connect | |||
RESERVED_TS | D5 | Output | LVCMOS | For proper DMD operation, do not connect | |||
LEAVE PIN UNCONNECTED | |||||||
NO CONNECT | B11 | For proper DMD operation, do not connect | |||||
NO CONNECT | C11 | For proper DMD operation, do not connect | |||||
NO CONNECT | C13 | For proper DMD operation, do not connect | |||||
NO CONNECT | E12 | For proper DMD operation, do not connect | |||||
NO CONNECT | E14 | For proper DMD operation, do not connect | |||||
NO CONNECT | E23 | For proper DMD operation, do not connect | |||||
NO CONNECT | H4 | For proper DMD operation, do not connect | |||||
NO CONNECT | N2 | For proper DMD operation, do not connect | |||||
NO CONNECT | N3 | For proper DMD operation, do not connect | |||||
NO CONNECT | N4 | For proper DMD operation, do not connect | |||||
NO CONNECT | R2 | For proper DMD operation, do not connect | |||||
NO CONNECT | R3 | For proper DMD operation, do not connect | |||||
NO CONNECT | R4 | For proper DMD operation, do not connect | |||||
NO CONNECT | T4 | For proper DMD operation, do not connect | |||||
NO CONNECT | U2 | For proper DMD operation, do not connect | |||||
NO CONNECT | U3 | For proper DMD operation, do not connect | |||||
NO CONNECT | U4 | For proper DMD operation, do not connect | |||||
NO CONNECT | W3 | For proper DMD operation, do not connect | |||||
NO CONNECT | W4 | For proper DMD operation, do not connect | |||||
NO CONNECT | W5 | For proper DMD operation, do not connect | |||||
NO CONNECT | W13 | For proper DMD operation, do not connect | |||||
NO CONNECT | W14 | For proper DMD operation, do not connect | |||||
NO CONNECT | W23 | For proper DMD operation, do not connect | |||||
NO CONNECT | X4 | For proper DMD operation, do not connect | |||||
NO CONNECT | X5 | For proper DMD operation, do not connect | |||||
NO CONNECT | X13 | For proper DMD operation, do not connect | |||||
NO CONNECT | Y2 | For proper DMD operation, do not connect | |||||
NO CONNECT | Y3 | For proper DMD operation, do not connect | |||||
NO CONNECT | Y4 | For proper DMD operation, do not connect | |||||
NO CONNECT | Y5 | For proper DMD operation, do not connect | |||||
NO CONNECT | Z11 | For proper DMD operation, do not connect |
PIN | TYPE (I/O/P) |
SIGNAL | DESCRIPTION | |
---|---|---|---|---|
NAME(1) | NO. | |||
VBIAS | A6, A7, A8, AA6, AA7, AA8 | Power | Analog | Supply voltage for positive Bias level of Micromirror reset signal. |
VOFFSET | A3, A4, A25 | Power | Analog | Supply voltage for HVCMOS logic. |
B26, L26, M26 | Power | Analog | Supply voltage for stepped high voltage at Micromirror address electrodes. | |
N26, Z26, AA3, AA4 | Power | Analog | Supply voltage for positive Offset level of Micromirror reset signal. | |
VRESET | G1, H1, J1, R1, T1, U1 | Power | Analog | Supply voltage for negative Reset level of Micromirror reset signal. |
VCC | A9, B3, B5, B12, C1, C6, C10, D4, D6, D8, E1, E2, E10, E15, E16, E17, F3, H2, K1, K3, M4, P1, P3, T2, V3, W1, W2, W6, W9, W10, W15, W16, W17, X3, X6, Y1, Y8, Y13, Z1, Z3, Z12, AA2, AA9, AA10 | Power | Analog | Supply voltage for LVCMOS core logic. Supply voltage for normal high level at Micromirror address electrodes. Supply voltage for positive Offset level of Micromirror reset signal during Power Down sequence. |
VCCI | A16, A17, A18, A20, A21, A23, AA16, AA17, AA18, AA20, AA21, AA23 | Power | Analog | Supply voltage for LVDS receivers. |
VSS | A5, A10, A11, A19, A22, A24, B2, B4, B9, B13, B17, B20, B21, B24, C7, C15, C18, C21, C22, C26, D1, D3, D7, D10, D12, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, D26, E6, E8, E18, E19, E20, E21, E22, E26, F1, F2, F4, F23, F26, G23, G26, H3, H26, J26, K2, K4, K26, L1, M1, M2, M3, M23, M24, M25, N1, P2, P4, P26, R26, T3, T26, U23, U26, V1, V2, V4, V23, V26, W8, W18, W19, W20, W21, W22, W26, X1, X2, X7, X10, X12, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X26, Y6, Y15, Y18, Y21, Y22, Y26, Z2, Z4, Z9, Z13, Z17, Z20, Z21, Z24, AA5, AA11, AA19, AA22, AA24 | Power | Analog | Device Ground. Common return for all power. |
SUPPLY VOLTAGES | MIN | MAX | UNIT | |
VCC | Supply voltage for LVCMOS core logic (2) | –0.5 | 4 | V |
VCCI | Supply voltage for LVDS receivers (2) | –0.5 | 4 | V |
VOFFSET | Supply voltage for HVCMOS and micromirror electrode (2) (3) | –0.5 | 9 | V |
VBIAS | Supply voltage for micromirror electrode (2) | –0.5 | 17 | V |
VRESET | Supply voltage for micromirror electrode (2) | –11 | 0.5 | V |
| VCC – VCCI | | Supply voltage delta (absolute value) (4) | 0.3 | V | |
| VBIAS – VOFFSET | | Supply voltage delta (absolute value) (5) | 8.75 | V | |
INPUT VOLTAGES | ||||
Input voltage for all other LVCMOS input pins (2) | –0.5 | VCC + 0.15 | V | |
Input voltage for all other LVDS input pins (2) (6) | –0.5 | VCCI + 0.15 | V | |
| VID | | Input differential voltage (absolute value) (7) | 700 | mV | |
IID | Input differential current (7) | 7 | mA | |
CLOCKS | ||||
ƒclock | Clock frequency for LVDS interface, DCLK (all channels) | 460 | MHz | |
ENVIRONMENTAL | ||||
TARRAY and TWINDOW | Temperature: operational (8) (9) | 0 | 90 | ºC |
Temperature: non–operational (9) | –40 | 90 | ||
|TDELTA| | Absolute temperature delta between any point on the window edge and the ceramic test point TP1(10) | 30 | ºC | |
TDP | Dew Point temperature, operating and non-operating (non-condensing) | 81 | ºC |
MIN | MAX | UNIT | ||
---|---|---|---|---|
TDMD | DMD Storage Temperature | –40 | 80 | °C |
TDP-AVG | Average dew point temperature (non-condensing) (1) | 28 | °C | |
TDP-ELR | Elevated dew point temperature range (non-condensing) (2) | 28 | 36 | °C |
CTELR | Cumulative time in elevated dew point temperature range | 24 | Months |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
SUPPLY VOLTAGES(1) (2) | |||||
VCC | Supply voltage for LVCMOS core logic | 3.15 | 3.3 | 3.45 | V |
VCCI | Supply voltage for LVDS receivers | 3.15 | 3.3 | 3.45 | V |
VOFFSET | Supply voltage for HVCMOS and micromirror electrodes(2) | 8.25 | 8.5 | 8.75 | V |
VBIAS | Supply voltage for micromirror electrodes | 15.5 | 16 | 16.5 | V |
VRESET | Supply voltage for micromirror electrodes | –9.5 | –10 | –10.5 | V |
|VCCI–VCC| | Supply voltage delta (absolute value) (3) | 0.3 | V | ||
|VBIAS–VOFFSET| | Supply voltage delta (absolute value)(4) | 8.75 | V | ||
LVCMOS PINS | |||||
VIH | High level Input voltage (5) | 1.7 | 2.5 | VCC + 0.15 | V |
VIL | Low level Input voltage(5) | – 0.3 | 0.7 | V | |
IOH | High level output current at VOH = 2.4 V | –20 | mA | ||
IOL | Low level output current at VOL = 0.4 V | 15 | mA | ||
TPWRDNZ | PWRDNZ pulse width(6) | 10 | ns | ||
SCP INTERFACE(7) | |||||
ƒclock | SCP clock frequency(8) | 500 | kHz | ||
tSCP_SKEW | Time between valid SCPDI and rising edge of SCPCLK(9) | –800 | 800 | ns | |
tSCP_DELAY | Time between valid SCPDO and rising edge of SCPCLK(9) | 700 | ns | ||
tSCP_BYTE_INTERVAL | Time between consecutive bytes | 1 | µs | ||
tSCP_NEG_ENZ | Time between falling edge of SCPENZ and the first rising edge of SCPCLK | 30 | ns | ||
tSCP_PW_ENZ | SCPENZ inactive pulse width (high level) | 1 | µs | ||
tSCP_OUT_EN | Time required for SCP output buffer to recover after SCPENZ (from tri-state) | 1.5 | ns | ||
ƒclock | SCP circuit clock oscillator frequency (10) | 9.6 | 11.1 | MHz | |
LVDS INTERFACE | |||||
ƒclock | Clock frequency for LVDS interface, DCLK (all channels) | 400 | MHz | ||
|VID| | Input differential voltage (absolute value)(11) | 100 | 400 | 600 | mV |
VCM | Common mode (11) | 1200 | mV | ||
VLVDS | LVDS voltage(11) | 0 | 2000 | mV | |
tLVDS_RSTZ | Time required for LVDS receivers to recover from PWRDNZ | 10 | ns | ||
ZIN | Internal differential termination resistance | 95 | 105 | Ω | |
ZLINE | Line differential impedance (PWB/trace) | 90 | 100 | 110 | Ω |
ENVIRONMENTAL (12) | |||||
TARRAY | Array temperature – operational, long-term (13) (14) (15) | 10 | 40 to 70(16) | °C | |
Array temperature – operational, short-term (13) (14) (17) | 0 | 10 | |||
TWINDOW | Window temperature – operational(18) | 85 | °C | ||
T|DELTA | | Absolute temperature delta between any point on the window edge and the ceramic test point TP1. (19) | 26 | °C | ||
TDP-AVG | Average dew point temperature (non-condensing) (20) | 28 | °C | ||
TDP-ELR | Elevated dew point temperature range (non-condensing) (21) | 28 | 36 | °C | |
CTELR | Cumulative time in elevated dew point temperature range | 24 | Months | ||
ILLUV | Illumination, wavelength < 420 nm | 0.68 | mW/cm2 | ||
ILLVIS | Illumination, wavelengths between 420 and 700 nm | Thermally Limited(22) | mW/cm2 | ||
ILLIR | Illumination, wavelength > 700 nm | 10 | mW/cm2 |
THERMAL METRIC(1) | DLP6500 | UNIT | |
---|---|---|---|
FYE (CPGA) | |||
350 PINS | |||
Active Area-to-Case Ceramic Thermal resistance (1) | 0.6 | °C/W |
PARAMETER | DESCRIPTION | TEST CONDITIONS(1) | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|---|
VOH | High-level output voltage | VCC = 3.0 V, IOH = –20 mA | 2.4 | V | ||
VOL | Low level output voltage | VCC = 3.45 V, IOL = 15 mA | 0.4 | V | ||
IIH | High–level input current(2) (3) | VCC = 3.45 V , VI = VCC | 250 | µA | ||
IlL | Low level input current | VCC = 3.45 V, VI = 0 | –250 | µA | ||
IOZ | High–impedance output current | VCC = 3.45 V | 10 | µA | ||
CURRENT | ||||||
ICC | Supply current (4) | VCC = 3.45 V | 1100 | mA | ||
ICCI | VCCI = 3.45 V | 510 | ||||
IOFFSET | Supply current (5) | VOFFSET = 8.75 V | 25 | mA | ||
IBIAS | VBIAS = 16.5 V | 14 | ||||
IRESET | Supply current | VRESET = –10.5 V | 11 | mA | ||
ITOTAL | Total Sum | 1660 | ||||
POWER | ||||||
PCC | Supply power dissipation | VCC = 3.45 V | 3960 | mW | ||
PCCI | VCCI = 3.45 V | 1836 | ||||
POFFSET | VOFFSET = 8.75 V | 219 | ||||
PBIAS | VBIAS = 16.5 V | 231 | ||||
PRESET | VRESET = –10.5 V | 116 | ||||
PTOTAL | Supply power dissipation(6) | Total Sum | 6362 | |||
CAPACITANCE | ||||||
CI | Input capacitance | ƒ = 1 MHz | 20 | pF | ||
CO | Output capacitance | ƒ = 1 MHz | 10 | pF | ||
CM | Reset group capacitance MBRST(14:0) | ƒ = 1 MHz all inputs interconnected, (1920 x 1080) array |
330 | 390 | pF |
DESCRIPTION(1) | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|
SCP INTERFACE(2) | |||||||
tr | Rise time | 20% to 80% | 200 | ns | |||
tƒ | Fall time | 80% to 20% | 200 | ns | |||
LVDS INTERFACE(2) | |||||||
tr | Rise time | 20% to 80% | 100 | 400 | ps | ||
tƒ | Fall time | 80% to 20% | 100 | 400 | ps | ||
LVDS CLOCKS(3) | |||||||
tc | Cycle time | DCLK_A, 50% to 50% | 2.5 | ns | |||
DCLK_B, 50% to 50% | 2.5 | ||||||
tw | Pulse duration | DCLK_A, 50% to 50% | 1.19 | 1.25 | ns | ||
DCLK_B, 50% to 50% | 1.19 | 1.25 | |||||
LVDS INTERFACE(3) | |||||||
tsu | Setup time | D_A(15:0) before rising or falling edge of DCLK_A | 0.1 | ns | |||
D_B(15:0) before rising or falling edge of DCLK_B | 0.1 | ||||||
tsu | Setup time | SCTRL_A before rising or falling edge of DCLK_A | 0.1 | ns | |||
SCTRL_B before rising or falling edge of DCLK_B | 0.1 | ||||||
th | Hold time | D_A(15:0) after rising or falling edge of DCLK_A | 0.4 | ns | |||
D_B(15:0) after rising or falling edge of DCLK_B | 0.4 | ||||||
th | Hold time | SCTRL_A after rising or falling edge of DCLK_A | 0.3 | ns | |||
SCTRL_B after rising or falling edge of DCLK_B | 0.3 | ||||||
LVDS INTERFACE(4) | |||||||
tskew | Skew time | Channel B relative to Channel A (4) | Channel A includes the following LVDS pairs: DCLK_AP and DCLK_AN SCTRL_AP and SCTRL_AN D_AP(15:0) and D_AN(15:0) |
–1.25 | 1.25 | ns | |
Channel B includes the following LVDS pairs: DCLK_BP and DCLK_BN SCTRL_BP and SCTRL_BN D_BP(15:0) and D_BN(15:0) |
Timing Diagrams
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. Figure 2 shows an equivalent test load circuit for the output under test. The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving.
Timing reference loads are not intended as a precise representation of any particular system environment or depiction of the actual load presented by a production test. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Refer to the Application and Implementation section.
In video mode, the video source is displayed on the DMD at the rate of the incoming video source.
In modes 2, 3, and 4, the pattern rates depend on the bit depth as shown in Table 1.
BIT DEPTH | VIDEO PATTERN MODE (Hz) | PRE-STORED or PATTERN ON-THE-FLY MODE (Hz) |
---|---|---|
1 | 2880 | 9523 |
2 | 1440 | 3289 |
3 | 960 | 2638 |
4 | 720 | 1364 |
5 | 480 | 823 |
6 | 480 | 672 |
7 | 360 | 500 |
8 | 247 | 247 |
When the DMD is controlled by the DLPC910, the digitial controller operates in 1-bit pattern mode only. With proper illumination modulation, bit depths greater than 1 can be achieved. Table 2 shows the pattern rates for each bit depth.
BIT DEPTH | PATTERN RATE (Hz) |
---|---|
1 | 11574 |
2 | 5787 |
3 | 3858 |
4 | 2893 |
5 | 2315 |
6 | 1929 |
7 | 1653 |
8 | 1446 |
PARAMETER | MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|---|
Maximum system mounting interface load(1) to be applied to the: | (See Figure 10) | kg | ||||
|
11.30 | |||||
11.30 | ||||||
Maximum Load Applied (2) | (See Figure 10) | kg | ||||
|
0 | |||||
22.60 |
VALUE | UNIT | ||||
---|---|---|---|---|---|
M | Number of active columns | See Figure 11 | 1920 | micromirrors | |
N | Number of active rows | 1080 | micromirrors | ||
P | Micromirror (pixel) pitch | 7.56 | µm | ||
Micromirror active array width | M × P | 14.5152 | mm | ||
Micromirror active array height | N × P | 8.1648 | mm | ||
Micromirror active border | Pond of micromirrors (POM)(1) | 14 | micromirrors /side |
See Optical Interface and System Image Quality for important information
PARAMETER | CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
α | Micromirror tilt angle | DMD landed state (1) | 12 | ° | ||
β | Micromirror tilt angle tolerance(1) (2) (3) (4) (5) | –1 | 1 | ° | ||
Micromirror tilt direction(5) (6) (7) | 44 | 45 | 46 | ° | ||
Number of out-of-specification micromirrors (8) | Adjacent micromirrors | 0 | micromirrors | |||
Non-adjacent micromirrors | 10 | |||||
Micromirror crossover time (9) (10) | Typical performance | 2.5 | μs | |||
DMD photopic efficiency within the wavelength range 420 nm to 700 nm (11) | 66% |
PARAMETER(1) | CONDITIONS | MIN | NOM | MAX | UNIT |
---|---|---|---|---|---|
Window material designation S600 | Corning Eagle XG | ||||
Window refractive index | at wavelength 546.1 nm | 1.5119 | |||
Window aperture | See (2) | ||||
Illumination overfill | Refer to Illumination Overfill | ||||
Window transmittance, single–pass through both surfaces and glass (3) | Minimum within the wavelength range 420 nm to 680 nm. Applies to all angles 0° to 30° AOI. | 97% | |||
Average over the wavelength range 420 nm to 680 nm. Applies to all angles 30° to 45° AOI. | 97% |
The DLP6500 is a component of one or more DLP chipsets. Reliable function and operation of the DLP6500 requires that it be used in conjunction with the other components of the applicable DLP chipset, including those components that contain or implement TI DMD control technology. TI DMD control technology are the TI technology and devices for operating or controlling a DLP DMD.
DLP6500 is a 0.65 inch diagonal spatial light modulator which consists of an array of highly reflective aluminum micromirrors. Pixel array size and square grid pixel arrangement are shown in Figure 11.
The DMD is an electrical input, optical output micro-electrical-mechanical system (MEMS). The electrical interface is Low Voltage Differential Signaling (LVDS), Double Data Rate (DDR).
DLP6500 DMD consists of a two-dimensional array of 1-bit CMOS memory cells. The array is organized in a grid of M memory cell columns by N memory cell rows. Refer to the Functional Block Diagram.
The positive or negative deflection angle of the micromirrors can be individually controlled by changing the address voltage of underlying CMOS addressing circuitry and micromirror reset signals (MBRST).
Each cell of the M × N memory array drives its true and complement (‘Q’ and ‘QB’) data to two electrodes underlying one micromirror, one electrode on each side of the diagonal axis of rotation. Refer to Micromirror Array Optical Characteristics. The micromirrors are electrically tied to the micromirror reset signals (MBRST) and the micromirror array is divided into reset groups.
Electrostatic potentials between a micromirror and its memory data electrodes cause the micromirror to tilt toward the illumination source in a DLP projection system or away from it, thus reflecting its incident light into or out of an optical collection aperture. The positive (+) tilt angle state corresponds to an 'on' pixel, and the negative (–) tilt angle state corresponds to an 'off' pixel.
Refer to Micromirror Array Optical Characteristics for the ± tilt angle specifications. Refer to Pin Configuration and Functions for more information on micromirror reset control.
DLP6500 device consists of highly reflective, digitally switchable, micrometer-sized mirrors (micromirrors) organized in a two-dimensional orthogonal pixel array. Refer to Figure 11 and Figure 13.
Each aluminum micromirror is switchable between two discrete angular positions, –α and +α. The angular positions are measured relative to the micromirror array plane, which is parallel to the silicon substrate. Refer to Micromirror Array Optical Characteristics and Figure 14.
The parked position of the micromirror is not a latched position and is therefore not necessarily perfectly parallel to the array plane. Individual micromirror flat state angular positions may vary. Tilt direction of the micromirror is perpendicular to the hinge-axis. The on-state landed position is directed toward the left-top edge of the package, as shown in Figure 13.
Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell contents, after the mirror clocking pulse is applied. The angular position (–α and +α) of the individual micromirrors changes synchronously with a micromirror clocking pulse, rather than being coincident with the CMOS memory cell data update.
Writing logic 1 into a memory cell followed by a mirror clocking pulse results in the corresponding micromirror switching to a +α position. Writing logic 0 into a memory cell followed by a mirror clocking pulse results in the corresponding micromirror switching to a – α position.
Updating the angular position of the micromirror array consists of two steps:
For more information, see the TI application report DLPA008A, DMD101: Introduction to Digital Micromirror Device (DMD) Technology.
DLP6500 is part of the chipset comprising of the DLP6500 DMD and DLPC900 display controller. To ensure reliable operation, DLP6500 DMD must always be used with a DLPC900 display controller.
DMD functional modes are controlled by the DLPC900 digital display controller. See the DLPC900 data sheet listed in Related Documents. Contact a TI applications engineer for more information.
NOTE
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system operating conditions exceeding limits described previously.
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment optical performance involves making trade-offs between numerous component and system design parameters. Optimizing system optical performance and image quality strongly relate to optical system design parameter trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical performance is contingent on compliance to the optical system operating conditions described in the following sections.
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the projection lens. The mirror tilt angle defines DMD capability to separate the "ON" optical path from any other light path, including undesirable flat-state specular reflections from the DMD window, DMD border structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination numerical aperture angle, objectionable artifacts in the display’s border and/or active area could occur.
TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally centered within 2° (two degrees) of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable artifacts in the display’s border and/or active area, which may require additional system apertures to control, especially if the numerical aperture of the system exceeds the pixel tilt angle.
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical operating conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window aperture opening and other surface anomalies that may be visible on the screen. The illumination optical system should be designed to limit light flux incident anywhere on the window aperture from exceeding approximately 10% of the average flux level in the active area. Depending on the particular system’s optical architecture, overfill light may have to be further reduced below the suggested 10% level in order to be acceptable.
Micromirror array temperature can be computed analytically from measurement points on the outside of the package, the ceramic package thermal resistance, the electrical power dissipation, and the illumination heat load. The relationship between micromirror array temperature and the reference ceramic temperature is provided by the following equations:
where
Electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating frequencies. The nominal electrical power dissipation to use when calculating array temperature is 2.9 Watts. Absorbed optical power from the illumination source is variable and depends on the operating state of the micromirrors and the intensity of the light source. Equations shown above are valid for a 1-chip DMD system with total projection efficiency through the projection lens from DMD to the screen of 87%.
The conversion constant CL2W is based on the DMD micromirror array characteristics. It assumes a spectral efficiency of 300 lm/W for the projected light and illumination distribution of 83.7% on the DMD active array, and 16.3% on the DMD array border and window aperture. The conversion constant is calculated to be 0.00293 W/lm.
Sample Calculation for typical projection application:
TCERAMIC = 55°C, assumed system measurement; see Recommended Operating Conditions for specific limits
SL = 2000 lm
QELECTRICAL = 2.9 W (see the maximum power specifications in Electrical Characteristics)
CL2W = 0.00293 W/lm
QARRAY = 2.9 W + (0.00293 W/lm × 2000 lm) = 8.76 W
TARRAY = 55°C + (8.76 W × 0.6 × C/W) = 60.26°C
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a percentage) that an individual micromirror is landed in the On–state versus the amount of time the same micromirror is landed in the Off–state.
As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the On–state 100% of the time (and in the Off–state 0% of the time); whereas 0/100 would indicate that the pixel is in the Off–state 100% of the time. Likewise, 50/50 indicates that the pixel is On 50% of the time and Off 50% of the time.
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other state (OFF or ON) is considered negligible and is thus ignored.
Since a micromirror can only be landed in one state or the other (On or Off), the two numbers (percentages) always add to 100.
Knowing the long-term average landed duty cycle (of the end product or application) is important because subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed duty cycle for a prolonged period of time can reduce the DMD’s usable life.
Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly asymmetrical.
Individual DMD mirror duty cycles vary by application as well as the mirror location on the DMD within any specific application. DMD mirror useful life are maximized when every individual mirror within a DMD approaches 50/50 (or 1/1) duty cycle. Therefore, for the DLPC900 and DLP6500 chipset, it is recommended that the DMD Idle Mode be enabled as often as possible. Examples are whenever the system is idle, the illumination is disabled, between sequential pattern exposures (if possible), or when the exposure pattern sequence is stopped for any reason. This software mode provides a 50/50 duty cycle across the entire DMD mirror array, where the mirrors are continuously flipped between the on and off states. Refer to the DLPC900 Software Programmer’s Guide DLPU018 for a description of the DMD Idle Mode command. For the DLPC910 and DLP6500 chipset, it is recommended that the controlling applications processor provide a 50/50 pattern sequence to the DLPC910 for display on the DLP6500 as often as possible, similar to the above examples stated for the DLPC900. The pattern provides a 50/50 duty cycle across the entire DMD mirror array, where the mirrors are continuously flipped between the on and off states.
Operational DMD Temperature and Landed Duty Cycle interact to affect the DMD’s usable life, and this interaction can be exploited to reduce the impact that an asymmetrical Landed Duty Cycle has on the DMD’s usable life. This is quantified in the de-rating curve shown in Figure 1. The importance of this curve is that:
In practice, this curve specifies the Maximum Operating DMD Temperature that the DMD should be operated at for a give long-term average Landed Duty Cycle.
During a given period of time, the Landed Duty Cycle of a given pixel follows from the image content being displayed by that pixel.
For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel will experience a 100/0 Landed Duty Cycle during that time period. Likewise, when displaying pure-black, the pixel will experience a 0/100 Landed Duty Cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an incoming image), the Landed Duty Cycle tracks one-to-one with the gray scale value, as shown in Table 3.
GRAYSCALE VALUE | LANDED DUTY CYCLE |
---|---|
0% | 0/100 |
10% | 10/90 |
20% | 20/80 |
30% | 30/70 |
40% | 40/60 |
50% | 50/50 |
60% | 60/40 |
70% | 70/30 |
80% | 80/20 |
90% | 90/10 |
100% | 100/0 |
Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from 0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a given primary must be displayed in order to achieve the desired white point.
During a given period of time, the landed duty cycle of a given pixel can be calculated as follows:
Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_% × Blue_Scale_Value)
Where:
Red_Cycle_%, Green_Cycle_%, and Blue_Cycle_%, represent the percentage of the frame time that Red, Green, and Blue are displayed (respectively) to achieve the desired white point.
For example, assume that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (in order to achieve the desired white point), then the Landed Duty Cycle for various combinations of red, green, blue color intensities would be as shown in Table 4.
Red Cycle Percentage 50% |
Green Cycle Percentage 20% |
Blue Cycle Percentage 30% |
Landed Duty Cycle |
---|---|---|---|
Red Scale Value | Green Scale Value | Blue Scale Value | |
0% | 0% | 0% | 0/100 |
100% | 0% | 0% | 50/50 |
0% | 100% | 0% | 20/80 |
0% | 0% | 100% | 30/70 |
12% | 0% | 0% | 6/94 |
0% | 35% | 0% | 7/93 |
0% | 0% | 60% | 18/82 |
100% | 100% | 0% | 70/30 |
0% | 100% | 100% | 50/50 |
100% | 0% | 100% | 80/20 |
12% | 35% | 0% | 13/87 |
0% | 35% | 60% | 25/75 |
12% | 0% | 60% | 24/76 |
100% | 100% | 100% | 100/0 |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The DLP6500 along with the DLPC900 controller provides a solution for many applications including structured light and video projection. The DMD is a spatial light modulator, which reflects incoming light from an illumination source to one of two directions, with the primary direction being into a projection or collection optic. Each application is derived primarily from the optical architecture of the system and the format of the data coming into the DLPC900. Applications of interest include machine vision and 3D printing.
A typical embedded system application using the DLPC900 controller and a DLP6500 is shown in Figure 16. In this configuration, the DLPC900 controller supports a 24-bit parallel RGB input, typical of LCD interfaces, from an external source or processor. This system configuration supports still and motion video sources plus sequential pattern mode. Refer to Related Documents for the DLPC900 digital controller data sheet.
A typical embedded system application using the DLPC910 digital controller and a DLP6500 is shown in Figure 17. In this configuration, the DLPC910 digital controller accepts streaming binary patterns from an external source or processor. This system configuration supports high speed pattern mode. Refer to Related Documents for the DLPC910 digital controller datasheet.
Detailed design requirements are located in the DLPC900 digital controller data sheet. Refer to Related Documents.
See the reference design schematic for connecting together the DLPC900 display controller and the DLP6500 DMD. An example board layout is included in the reference design data base. Layout guidelines should be followed for reliability.
See the reference design schematic for connecting together the DLPC910 controller and the DLP6500 DMD. An example board layout is included in the reference design data base. Layout guidelines should be followed for reliability.