JAJSKY2A November   2017  – February 2023 DLP650LE

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Capacitance at Recommended Operating Conditions
    8. 6.8  Timing Requirements
    9. 6.9  Window Characteristics
    10. 6.10 System Mounting Interface Loads
    11. 6.11 Micromirror Array Physical Characteristics
    12. 6.12 Micromirror Array Optical Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
  10. 10Device and Documentation Support
    1. 10.1 サード・パーティ製品に関する免責事項
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
    4. 10.4 ドキュメントの更新通知を受け取る方法
    5. 10.5 サポート・リソース
    6. 10.6 Trademarks
    7. 10.7 静電気放電に関する注意事項
    8. 10.8 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2 DMD Power Supply Power-Down Procedure

  • During power-down, VCC and VCCI must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within the specified limit of ground. See Table 9-2.
  • During power-down, it is a strict requirement that the voltage delta between VBIAS and VOFFSET must be within the specified limit shown in Section 6.4.
  • During power-down, there is no requirement for the relative timing of VRESET with respect to VBIAS.
  • Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the requirements specified in Section 6.1, in Section 6.4, and in Figure 9-1.
  • During power-down, LVCMOS input pins must be less than specified in Section 6.4.
Table 9-1 DMD Power Supply Transition Points
TIMEDESCRIPTION
t1DLP controller software enables the DMD power supplies to turn on after RESET_OEZ is at logic high
t1PG_OFFSET turns OFF after EN_OFFSET turns OFF per the tD2 specification in Table 9-2.
t2DLP controller software initiates the global VBIAS command.
t3After the DMD micromirror park sequence is complete, the DLP controller software initiates a hardware power-down that activates PWRDNZ and disables VBIAS, VRESET and VOFFSET.
t4Under power-loss conditions where emergency DMD micromirror park procedures are being enacted by the DLP controller hardware, EN_OFFSET may turn off after PG_OFFSET has turned off. The OEZ signal should go high prior to PG_OFFSET turning off to indicate the DMD micromirror has completed the emergency park procedures.
GUID-EC28374B-18F8-49E1-8B8F-D518C7C5C56C-low.gif
  1. Not to scale. Some details omitted for clarity. See Section 6.4 for all specified limits and Section 5 table for pin descriptions.
  2. To prevent excess current, the supply voltage difference |VCCI – VCC| must be less than the specified limit.
  3. To prevent excess current, the supply voltage difference |VBIAS – VOFFSET| must be less than the specified limit.
  4. To prevent excess current, the supply voltage difference |VBIAS – VRESET| must be less than the specified limit.
  5. See Table 9-2 for delay time descriptions.
  6. See Table 9-1 for transition time point descriptions.
Figure 9-1 Power Supply Timing(1)
Table 9-2 Delay Times Requirements
DELAY TIMEDESCRIPTIONMINNOMMAXUNIT
tD1Delay time period from VOFFSET settled at recommended operating voltage to VBIAS and VRESET power up.12ms
tD2Delay time period between PG_OFFSET hold time and when EN_OFFSET goes low100ns