JAJSKY2 データシート

JAJSKY2A November 2017 – February 2023 DLP650LE

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

FYL|149
- MCLG035

サーマルパッド・メカニカル・データ

発注情報

jajsky2a_oa

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted).⁽¹⁾

		MIN	MAX	UNIT
SUPPLY VOLTAGES
V_CC	Supply voltage for LVCMOS core logic⁽²⁾	–0.5	4	V
V_CCI	Supply voltage for LVDS Interface⁽²⁾	–0.5	4	V
V_OFFSET	Micromirror Electrode and HVCMOS voltage⁽²⁾⁽³⁾	–0.5	9	V
V_MBRST	Input voltage for MBRST(15:0)⁽²⁾	–28	28	V
\|V_CCI – V_CC\|	Supply voltage delta (absolute value)⁽⁴⁾		0.3	V
INPUT VOLTAGES
	Input voltage for all other input pins⁽²⁾	–0.5	V_CC + 0.3	V
\|V_ID\|	Input differential voltage (absolute value)⁽⁵⁾		700	mV
CLOCKS
ƒ_CLOCK	Clock frequency for LVDS interface, DCLK_A		400	MHz
ƒ_CLOCK	Clock frequency for LVDS interface, DCLK_B		400	MHz
ENVIRONMENTAL
T_ARRAY and T_WINDOW	Temperature, operating⁽⁶⁾	0	90	°C
T_ARRAY and T_WINDOW	Temperature, non–operating⁽⁶⁾	–40	90	°C
\|T_DELTA\|	Absolute Temperature delta between any point on the window edge and the ceramic test point TP1⁽⁷⁾		30	°C
T_DP	Dew point temperature, operating and non–operating (noncondensing)		81	°C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltages are referenced to common ground V_SS. V_BIAS, V_CC, V_CCI, V_OFFSET, and V_RESET power supplies are all required for all DMD operating modes.

(3) V_OFFSET supply transients must fall within specified voltages.

(4) Exceeding the recommended allowable voltage difference between V_CC and V_CCI may result in excessive current draw.

(5) The maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.

(6) The highest temperature of the active array (as calculated using Section 7.6) or of any point along the window edge as defined in Figure 7-1. The locations of thermal test points TP2, TP3, TP4, and TP5 in Figure 7-1 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, then that point should be used.

(7) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in Figure 7-1. The window test points TP2, TP3, TP4, and TP5 shown in Figure 7-1 are intended to result in the worst-case delta. If a particular application causes another point on the window edge to result in a larger delta temperature, then that point should be used.