JAJSGK2 データシート

JAJSGK2 November 2018 DLP650LNIR

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

FYL|149
- MCLG035

サーマルパッド・メカニカル・データ

発注情報

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is implied when operating the device above or below these limits.

		MIN	NOM	MAX	UNIT
VOLTAGE SUPPLY
V_CC	Supply voltage for LVCMOS core logic⁽¹⁾	3.0	3.3	3.6	V
V_CCI	Supply voltage for LVDS Interface⁽¹⁾	3.0	3.3	3.6	V
V_CC2	Micromirror Electrode and HVCMOS voltage⁽¹⁾⁽²⁾	8.25	8.5	8.75	V
V_MBRST	Micromirror Bias / Reset Voltage⁽¹⁾	–27		26.5	V
\|V_CC – V_CCI\|	Supply voltage delta (absolute value)⁽³⁾		0	0.3	V
LVCMOS INTERFACE
V_IH	Input High Voltage	1.7	2.5	V_CC + 0.3	V
V_IL	Input Low Voltage	–0.3		0.7	V
I_OH	High Level Output Current			–20	mA
I_OL	Low Level Output Current			15	mA
t_PWRDNZ	PWRDNZ pulse width⁽⁴⁾	10			ns
SCP INTERFACE
ƒ_SCPCLK	SCP clock frequency⁽⁵⁾	50		500	kHz
t_{SCP_PD}	Propagation delay, clock to Q, from rising-edge of SCPCLK to valid SCPDO.⁽⁶⁾	0		900	ns
t_{SCP_DS}	SCPDI clock setup time (before SCPCLK falling-edge)⁽⁶⁾	800			ns
t_{SCP_DH}	SCPDI hold time (after SCPCLK falling-edge)⁽⁶⁾	900			ns
t_{SCP_NEG_ENZ}	Time between falling–edge of SCPENZ and the rising–edge of SCPCLK.⁽⁵⁾	1			us
_{SCP_POS_ENZ}	Time between falling-edge of SCPCLK and the rising–edge of SCPENZ	1			us
t_{SCP_OUT_EN}	Time required for SCP output buffer to recover after SCPENZ (from tri-state).			192/ƒ_DCLK	s
t_{SCP_PW_ENZ}	SCPENZ inactive pulse width (high level)	1			1/ƒ_scpclk
t_r	Rise Time (20% to 80%). See ⁽⁶⁾			200	ns
t_f	Fall time (80% to 20%). See ⁽⁶⁾			200	ns
LVDS INTERFACE
ƒ_CLOCK	Clock frequency for LVDS interface (all channels), DCLK⁽⁷⁾	395	400	405	MHz
\|V_ID\|	Input differential voltage (absolute value)⁽⁸⁾	100	400	600	mV
V_CM	Common mode voltage⁽⁸⁾		1200		mV
V_LVDS	LVDS voltage⁽⁸⁾	0		2000	mV
t_{LVDS_RSTZ}	Time required for LVDS receivers to recover from PWRDNZ			10	ns
Z_IN	Internal differential termination resistance	95		105	Ω
Z_LINE	Line differential impedance (PWB/trace)	90	100	110	Ω
ENVIRONMENTAL
T_MIRROR	Micromirror temperature, long–term operational⁽⁹⁾⁽¹⁰⁾⁽¹¹⁾	10		40 to 70⁽¹²⁾	°C
T_MIRROR	Micromirror temperature, short–term operational⁽¹⁰⁾⁽¹³⁾	0		10	°C
T_WINDOW	Window temperature–operational⁽¹⁴⁾	10		85	°C
T_{\|DELTA \|}	Absolute temperature delta between any point on the window edge and the ceramic test point TP1. ⁽¹⁵⁾			26	°C
T_{DP -AVG}	Average dew point temperature (non–condensing)⁽¹⁶⁾			28	°C
T_DP-ELR	Elevated dew point temperature range (non-condensing)⁽¹⁷⁾	28		36	°C
CT_ELR	Cumulative time in elevated dew point temperature range			24	Months
ILL_UV	Illumination Power Density < 420 nm⁽⁹⁾			10	mW/cm²
ILL_VIS-NIR	Illumination Power Density between 420 nm and 950 nm			40	W/cm²
ILL_NIR2A	Illumination Total Power between 950 nm and 1150 nm⁽¹⁸⁾			160	W
ILL_NIR2B	Illumination Power Density between 950 nm and 1150 nm⁽¹⁸⁾			500	W/cm²
ILL_NIR3	Illumination Power Density between 1150 nm and 2000 nm			40	W/cm²
ILL_IR	Illumination Power Density > 2000 nm			10	mW/cm²

(1) All voltages are referenced to V_SS (common ground). V_CC, V_CCI, V_CC2, and V_MBRST power supplies are all required for proper DMD operation. V_SS must also be connected to common ground.

(2) V_CC2 supply transients must fall within specified max voltages.

(3) To prevent excess current, the supply voltage delta |V_CCI – V_CC| must be less than the specified limit.

(4) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tri-states the SCPDO output pin.

(5) The SCP clock is a gated clock. Duty cycle must be 50% ± 10%. SCP parameter is related to the frequency of DCLK.

(6) See Figure 3.

(7) See LVDS Timing Requirements in Timing Requirements and Figure 7.

(8) See Figure 6 LVDS Waveform Requirements.

(9) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination reduces device lifetime.

(10) The mirror temperatures cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1) shown in Figure 20 and the DMD package and mirror thermal resistances using the Micromirror Temperature Calculations.

(11) Long-term is defined as the usable life of the device.

(12) Per Figure 2, derate the maximum operational micromirror temperature based on the micromirror landed duty cycle that the DMD experiences in the end application. See Micromirror Landed-On/Landed-Off Duty Cycle for a definition of micromirror landed duty cycle.

(13) Mirror temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up). Short-term is defined as cumulative time over the usable life of the device and is less than 500 hours.

(14) The locations of thermal test points TP2, TP3, TP4, and TP5 in Figure 20 are intended to measure the highest window edge temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular application causes additional points on the window edge to be at a higher temperature, add test points to those locations.

(15) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in Figure 20. The window test points TP2, TP3, TP4, and TP5 shown in Figure 20 are intended to result in the worst case delta temperature. If a particular application causes another point on the window edge to result in a larger delta temperature, use that point.

(16) The average over time (including storage and operating) that the device is not in the ‘elevated dew point temperature range'.

(17) Limit exposure to dew point temperatures in the elevated range during storage and operation to less than a total cumulative time of CT_ELR.

(18) See Figure 1 for allowable combinations of illumination power vs illumination power density. 160W total power is achievable only by full array illumination. 500 W/cm² is only achievable through partial array illumination. Some combinations of illumination power and power density require cooling of the window with forced air as defined by Figure 1. Refer to the application note DLP® High Power Thermal Design Guide: Focus on High Power NIR Laser Illumination for additional details.

Figure 1. Maximum Recommended Illumination Incident Power vs Incident Irradiance

DLP650LNIR max_rec_mirror_temp_derating_curve.gif

Figure 2. Maximum Recommended Micromirror Temperature - Derating Curve (see Landed Duty Cycle and Operational DMD Temperature)