JAJSPX6A August   2017  – February 2023 DLP650NE

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Window Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On or Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On or Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
        1.       Application and Implementation
          1. 8.1 Application Information
          2. 8.2 Typical Application
            1. 8.2.1 Design Requirements
            2. 8.2.2 Detailed Design Procedure
  8. 8 Power Supply Requirements
    1. 8.1 DMD Power Supply Requirements
    2. 8.2 DMD Power Supply Power-Up Procedure
    3. 8.3 DMD Power Supply Power-Down Procedure
  9. 9 Device Documentation Support
    1. 9.1 サード・パーティ製品に関する免責事項
    2. 9.2 Device Support
      1. 9.2.1 Device Nomenclature
      2. 9.2.2 Device Markings
    3. 9.3 Documentation Support
      1. 9.3.1 Related Documentation
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 サポート・リソース
    6. 9.6 Trademarks
    7. 9.7 静電気放電に関する注意事項
    8. 9.8 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • FYE|350
サーマルパッド・メカニカル・データ
発注情報

8.3 DMD Power Supply Power-Down Procedure

  • During power-down, VCC and VCCI must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within the specified limit of ground. Refer to Table 8-1.
  • During power-down, it is a strict requirement that the change between VBIAS and VOFFSET must be within the specified limit shown in the Recommended Operating Conditions table. During power-down, it is not mandatory to stop driving VBIAS prior to VOFFSET.
  • During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and VBIAS.
  • Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the requirements listed in Absolute Maximum Ratings, in Recommended Operating Conditions, and in Figure 8-1.
  • During power-down, LVCMOS input pins must be less than specified in the Recommended Operating Conditions table.
GUID-0EC85372-A976-4E43-A9BD-8EA947849E21-low.gifFigure 8-1 DMD Power Supply Sequencing Requirements
A. To prevent excess current, the supply voltage change |VBIAS – VOFFSET| must be less than specified in the Recommended Operating Conditions table. OEMs may find that the most reliable way to ensure this is to power VOFFSET prior to VBIAS during power-up and to remove VBIAS prior to VOFFSET during power-down.
B. LVDS signals are less than the input differential voltage (VID) maximum specified in the Recommended Operating Conditions table. During power-down, LVDS signals are less than the high level input voltage (VIH) maximum specified in the Recommended Operating Conditions table.
C. When system power is interrupted, the DLP DLPC4430 initiates a hardware power-down that activates PWRDNZ and disables VBIAS, VRESET and VOFFSET after the micromirror park sequence. Software power-down disables VBIAS, VRESET, and VOFFSET after the micromirror park sequence through software control. For either case, enable signals EN_BIAS, EN_OFFSET, and EN_RESET are used to disable VBIAS, VOFFSET, and VRESET, respectfully.
D. Refer to Table 8-1.
E. Figure not to scale. Details have been omitted for clarity. Refer to the Recommended Operating Conditions table.
F. EN_BIAS, EN_OFFSET, and EN_RESET are disabled by DLP controller software or PWRDNZ signal control.
G. VBIAS, VOFFSET, and VRESET are disabled by DLP controller software.
Table 8-1 DMD Power-Down Sequence Requirements
PARAMETERMINMAXUNIT
VBIASSupply voltage level during power–down sequence4.0V
VOFFSET4.0V
VRESET–4.00.5V