JAJSPX6A August   2017  – February 2023 DLP650NE

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Window Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On or Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On or Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
        1.       Application and Implementation
          1. 8.1 Application Information
          2. 8.2 Typical Application
            1. 8.2.1 Design Requirements
            2. 8.2.2 Detailed Design Procedure
  8. 8 Power Supply Requirements
    1. 8.1 DMD Power Supply Requirements
    2. 8.2 DMD Power Supply Power-Up Procedure
    3. 8.3 DMD Power Supply Power-Down Procedure
  9. 9 Device Documentation Support
    1. 9.1 サード・パーティ製品に関する免責事項
    2. 9.2 Device Support
      1. 9.2.1 Device Nomenclature
      2. 9.2.2 Device Markings
    3. 9.3 Documentation Support
      1. 9.3.1 Related Documentation
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 サポート・リソース
    6. 9.6 Trademarks
    7. 9.7 静電気放電に関する注意事項
    8. 9.8 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • FYE|350
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-B8E1000E-47DE-44C2-8652-AEFBBE7E2951-low.gif Figure 5-1 FYE Package350-PinBottom View
Table 5-1 Pin Functions
PIN(1) TYPE(5) SIGNAL DATA RATE(2) INTERNAL TERM(3) DESCRIPTION TRACE (mils)(4)
NAME NO.
DATA BUS A
D_AN(0) B14 I LVDS DDR Differential Data, negative 494.88
D_AN(1) B15 I DDR Differential Data, negative 486.18
D_AN(2) C16 I DDR Differential Data, negative 495.16
D_AN(3) K24 I DDR Differential Data, negative 485.67
D_AN(4) B18 I DDR Differential Data, negative 494.76
D_AN(5) L24 I DDR Differential Data, negative 490.63
D_AN(6) C19 I DDR Differential Data, negative 495.16
D_AN(7) H24 I DDR Differential Data, negative 485.55
D_AN(8) H23 I DDR Differential Data, negative 495.16
D_AN(9) B25 I DDR Differential Data, negative 485.59
D_AN(10) D24 I DDR Differential Data, negative 495.16
D_AN(11) E25 I DDR Differential Data, negative 495.16
D_AN(12) F25 I DDR Differential Data, negative 490.04
D_AN(13) H25 I DDR Differential Data, negative 485.91
D_AN(14) L25 I DDR Differential Data, negative 495.16
D_AN(15) G24 I DDR Differential Data, negative 495.16
D_AP(0) C14 I LVDS DDR Differential Data, positive 494.84
D_AP(1) B16 I DDR Differential Data, positive 486.22
D_AP(2) C17 I DDR Differential Data, positive 494.65
D_AP(3) K23 I DDR Differential Data, positive 488.42
D_AP(4) B19 I DDR Differential Data, positive 495.16
D_AP(5) L23 I DDR Differential Data, positive 490.67
D_AP(6) C20 I DDR Differential Data, positive 498.11
D_AP(7) J24 I DDR Differential Data, positive 486.22
D_AP(8) J23 I DDR Differential Data, positive 495.47
D_AP(9) C25 I DDR Differential Data, positive 485.94
D_AP(10) E24 I DDR Differential Data, positive 495.16
D_AP(11) D25 I DDR Differential Data, positive 494.13
D_AP(12) G25 I DDR Differential Data, positive 488.98
D_AP(13) J25 I DDR Differential Data, positive 492.56
D_AP(14) K25 I DDR Differential Data, positive 495.16
D_AP(15) F24 I DDR Differential Data, positive 495.16
DATA BUS B
D_BN(0) Z14 I LVDS DDR Differential Data, negative 494.92
D_BN(1) Z15 I DDR Differential Data, negative 486.18
D_BN(2) Y16 I DDR Differential Data, negative 496.46
D_BN(3) P24 I DDR Differential Data, negative 493.74
D_BN(4) Z18 I DDR Differential Data, negative 494.76
D_BN(5) N24 I DDR Differential Data, negative 495.16
D_BN(6) Y19 I DDR Differential Data, negative 492.16
D_BN(7) T24 I DDR Differential Data, negative 492.68
D_BN(8) T23 I DDR Differential Data, negative 484.45
D_BN(9) Z25 I DDR Differential Data, negative 492.09
D_BN(10) X24 I DDR Differential Data, negative 497.72
D_BN(11) W25 I DDR Differential Data, negative 495.16
D_BN(12) V25 I DDR Differential Data, negative 484.17
D_BN(13) T25 I DDR Differential Data, negative 481.42
D_BN(14) N25 I DDR Differential Data, negative 495.16
D_BN(15) U24 I DDR Differential Data, negative 489.8
D_BP(0) Y14 I LVDS DDR Differential Data, positive 494.88
D_BP(1) Z16 I DDR Differential Data, positive 486.26
D_BP(2) Y17 I DDR Differential Data, positive 495.16
D_BP(3) P23 I DDR Differential Data, positive 492.48
D_BP(4) Z19 I DDR Differential Data, positive 495.16
D_BP(5) N23 I DDR Differential Data, positive 497.99
D_BP(6) Y20 I DDR Differential Data, positive 495.16
D_BP(7) R24 I DDR Differential Data, positive 492.05
D_BP(8) R23 I DDR Differential Data, positive 484.45
D_BP(9) Y25 I DDR Differential Data, positive 492.24
D_BP(10) W24 I DDR Differential Data, positive 495.16
D_BP(11) X25 I DDR Differential Data, positive 494.72
D_BP(12) U25 I DDR Differential Data, positive 483.78
D_BP(13) R25 I DDR Differential Data, positive 489.13
D_BP(14) P25 I DDR Differential Data, positive 499.53
D_BP(15) V24 I DDR Differential Data, positive 488.66
SERIAL CONTROL
SCTRL_AN C23 I LVDS DDR Differential Serial control, negative 492.95
SCTRL_BN Y23 I DDR Differential Serial control, negative 493.78
SCTRL_AP C24 I DDR Differential Serial control, negative 493.78
SCTRL_BP Y24 I DDR Differential Serial control, negative 493.11
CLOCKS
DCLK_AN B23 I LVDS Differential Clock, negative 480.35
DCLK_BN Z23 I Differential Clock, negative 486.22
DCLK_AP B22 I Differential Clock, negative 485.83
DCLK_BP Z22 I Differential Clock, negative 491.93
SERIAL COMMUNICATIONS PORT (SCP)
SCP_DO B8 O LVCMOS SDR Serial communications port output
SCP_DI B7 I SDR Pulldown Serial communication port data I
SCP_CLK B6 I Serial communications port clock
SCP_ENZ C8 I Active-low serial communications port enable
MICROMIRROR RESET CONTROL
RESET_ADDR(0) X9 I LVCMOS Pulldown Reset driver address select
RESET_ADDR(1) X8 I Reset driver address select
RESET_ADDR(2) Z8 I Reset driver address select
RESET_ADDR(3) Z7 I Reset driver address select
RESET_MODE(0) W11 I Reset driver mode select
RESET_MODE(1) Z10 I Reset driver mode select
RESET_SEL(0) Y10 I Reset driver level select
RESET_SEL(1) Y9 I Reset driver level select
RESET_STROBE Y7 I Reset address, mode, and level latched on rising-edge
ENABLES AND INTERRUPTS
PWRDNZ D2 I LVCMOS Pulldown Active-low device reset
RESET_OEZ W7 I Pulldown Active-low output enable for DMD reset driver circuits
RESETZ Z6 I Pulldown Active-low sets reset circuits in known VOFFSET state
RESET_IRQZ Z5 O Active-low, output interrupt to ASIC
VOLTAGE REGULATOR MONITORING
PG_BIAS E11 I LVCMOS Pullup Active-low fault from external VBIAS regulator
PG_OFFSET B10 I Active-low fault from external VOFFSET regulator
PG_RESET D11 I Active low from external VRESET regulator
EN_BIAS D9 O Active-high enable for external VBIAS regulator
EN_OFFSET C9 O Active-high enable for external VOFFSET regulator
EN_RESET E9 O Active-high enable for external VRESET regulator
LEAVE PIN UNCONNECTED
MBRST(0) C2 O Analog Pulldown For proper DMD operation, do not connect.
MBRST(1) C3 O
MBRST(2) C5 O
MBRST(3) C4 O
MBRST(4) E5 O
MBRST(5) E4 O
MBRST(6) E3 O
MBRST(7) G4 O
MBRST(8) G3 O
MBRST(9) G2 O
MBRST(10) J4 O
MBRST(11) J3 O
MBRST(12) J2 O
MBRST(13) L4 O
MBRST(14) L3 O
MBRST(15) L2 O
LEAVE PIN UNCONNECTED
RESERVED_PFE E7 I LVCMOS Pulldown For proper DMD operation, do not connect.
RESERVED_TM D13 I
RESERVED_Xl1 E13 I
RESERVED_TP0 W12 I Analog
RESERVED_TP1 Y11 I
RESERVED_TP2 X11 I
LEAVE PIN UNCONNECTED
RESERVED_BA Y12 O LVCMOS For proper DMD operation, do not connect.
RESERVED_BB C12 O
RESERVED_TS D5 O
LEAVE PIN UNCONNECTED
NO CONNECT B11 For proper DMD operation, do not connect.
NO CONNECT C11
NO CONNECT C13
NO CONNECT E12
NO CONNECT E14
NO CONNECT E23
NO CONNECT H4 For proper DMD operation, do not connect.
NO CONNECT N2
NO CONNECT N3
NO CONNECT N4
NO CONNECT R2
NO CONNECT R3
NO CONNECT R4
NO CONNECT T4
NO CONNECT U2 For proper DMD operation, do not connect.
NO CONNECT U3
NO CONNECT U4
NO CONNECT W3
NO CONNECT W4
NO CONNECT W5
NO CONNECT W13
NO CONNECT W14
NO CONNECT W23
NO CONNECT X4 For proper DMD operation, do not connect.
NO CONNECT X5
NO CONNECT X13
NO CONNECT Y2
NO CONNECT Y3
NO CONNECT Y4
NO CONNECT Y5
NO CONNECT Z11
(1) The following power supplies are required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET. VSS must also be connected.
(2) DDR = Double Data Rate. SDR = Single Data Rate. Refer to Section 6.7 for specifications and relationships.
(3) Internal term—CMOS level internal termination. Refer to Section 6.4 for differential termination specification.
(4) Dielectric Constant for the DMD FYE package is approximately 9.6. For the package trace lengths shown: Propagation Speed = 11.8 / sqrt(9.6) = 3.808 in/ns. Propagation Delay = 0.262 ns/in = 262 ps/in = 10.315 ps/mm.
(5) I = Input, O = Output, G = Ground
Table 5-2 Power Pin Functions
PIN TYPE (I/O/P)(2) SIGNAL DESCRIPTION
NAME(1) NO.
VBIAS A6, A7, A8, AA6, AA7, AA8 P Analog Supply voltage for positive Bias level of micromirror reset signal
VOFFSET A3, A4, A25 Analog Supply voltage for HVCMOS logic
B26, L26, M26 Analog Supply voltage for stepped high voltage at micromirror address electrodes
N26, Z26, AA3, AA4 Analog Supply voltage for positive Offset level of micromirror reset signal
VRESET G1, H1, J1, R1, T1, U1 Analog Supply voltage for negative Reset level of micromirror reset signal
VCC A9, B3, B5, B12, C1, C6, C10, D4, D6, D8, E1, E2, E10, E15, E16, E17, F3, H2, K1, K3, M4, P1, P3, T2, V3, W1, W2, W6, W9, W10, W15, W16, W17, X3, X6, Y1, Y8, Y13, Z1, Z3, Z12, AA2, AA9, AA10 Analog Supply voltage for LVCMOS core logic. Supply voltage for normal high level at micromirror address electrodes. Supply voltage for positive Offset level of micromirror reset signal during power-down sequence
VCCI A16, A17, A18, A20, A21, A23, AA16, AA17, AA18, AA20, AA21, AA23 Analog Supply voltage for LVDS receivers
VSS A5, A10, A11, A19, A22, A24, B2, B4, B9, B13, B17, B20, B21, B24, C7, C15, C18, C21, C22, C26, D1, D3, D7, D10, D12, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, D26, E6, E8, E18, E19, E20, E21, E22, E26, F1, F2, F4, F23, F26, G23, G26, H3, H26, J26, K2, K4, K26, L1, M1, M2, M3, M23, M24, M25, N1, P2, P4, P26, R26, T3, T26, U23, U26, V1, V2, V4, V23, V26, W8, W18, W19, W20, W21, W22, W26, X1, X2, X7, X10, X12, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X26, Y6, Y15, Y18, Y21, Y22, Y26, Z2, Z4, Z9, Z13, Z17, Z20, Z21, Z24, AA5, AA11, AA19, AA22, AA24 Analog Device ground. Common return for all power
(1) The following power supplies are required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET. VSS must also be connected.
(2) P = Power