JAJSLH9 データシート

JAJSLH9A March 2021 – May 2022 DLP650TE

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

FYP|149
- MCLG039

サーマルパッド・メカニカル・データ

発注情報

jajslh9a_oa

6.4 Recommended Operating Conditions

Over operating free-air temperature range and supply voltages (unless otherwise noted) ⁽¹⁾

Parameter Name		MIN	NOM	MAX	UNIT
Supply Voltages ⁽²⁾ ⁽³⁾
V_DD	Supply voltage for LVCMOS core logic and low speed interface (LSIF)	1.71	1.8	1.95	V
V_DDA	Supply voltage for high speed serial interface (HSSI) receivers	1.71	1.8	1.95	V
V_OFFSET	Supply voltage for HVCMOS and micromirror electrode ⁽⁴⁾	9.5	10	10.5	V
V_BIAS	Supply voltage for micromirror electrode	15.5	16	16.5	V
V_RESET	Supply voltage for micromirror electrode	–12.5	–12	–11.5	V
\| V_DDA – V_DD \|	Supply voltage delta, absolute value ⁽⁵⁾			0.3	V
\| V_BIAS – _VOFFSET \|	Supply voltage delta, absolute value ⁽⁶⁾			10.5	V
\| V_BIAS – V_RESET \|	Supply voltage delta, absolute value			29	V
LVCMOS Input
V_IH	High level input voltage ⁽⁷⁾	0.7 x V_DD			V
V_IL	Low level input voltage ⁽⁷⁾			0.3 x V_DD	V
Low Speed Interface (LSIF)
f_CLOCK	LSIF clock frequency (LS_CLK) ⁽⁸⁾	108	120	130	MHz
DCD_IN	LSIF duty cycle distortion (LS_CLK)	44%		56%
\| V_ID \|	LSIF differential input voltage magnitude ⁽⁸⁾	150	350	440	mV
V_LVDS	LSIF voltage. ⁽⁸⁾	575		1520	mV
V_CM	Common mode voltage. ⁽⁸⁾	700	900	1300	mV
Z_LINE	Line differential impedance (PWB/trace)	90	100	110	Ω
Z_IN	Internal differential termination resistance	80	100	120	Ω
High Speed Serial Interface (HSSI)
f_CLOCK	HSSI clock frequency (DCLK) ⁽⁹⁾	1.2		1.6	GHz
DCD_IN	HSSI duty cycle distortion (DCLK)	44%	50%	56%
\| V_ID \| Data	HSSI differential input voltage magnitude Data Lane ⁽⁹⁾	100		600	mV
\| V_ID \| CLK	HSSI differential input voltage magnitude Clock Lane ⁽⁹⁾	295		600	mV
VCM_DCData	Input common mode voltage (DC) Data Lane ⁽⁹⁾	200	600	800	mV
VCM_DC CLK	Input common mode voltage (DC) Clk Lane ⁽⁹⁾	200	600	800	mV
VCM_ACp-p	AC peak to peak (ripple) on common mode voltage of Data Lane and Clock Lane ⁽⁹⁾			100	mV
Z_LINE	Line differential impedance (PWB/trace)		100		Ω
Z_IN	Internal differential termination resistance. ( R_Xterm )	80	100	120	Ω
Environmental
T_ARRAY	Array temperature, long-term operational. ⁽¹⁰⁾⁽¹¹⁾⁽¹²⁾⁽¹³⁾	10		40 to 70	°C
T_ARRAY	Array temperature, short-term operational, 500 hr max. ⁽¹¹⁾⁽¹⁴⁾	0		10	°C
T_DP-AVG	Average dew point temperature (non-condensing)⁽¹⁵⁾			28	°C
T_DP-ELR	Elevated dew point temperature range (non-condensing)⁽¹⁶⁾	28		36	°C
CT_ELR	Cumulative time in elevated dew point temperature range			24	Months
Q_AP-ILL	Window aperture illumination overfill⁽¹⁷⁾⁽¹⁸⁾			17	W/cm²
LAMP ILLUMINATION
ILL_UV	Illumination wavelength < 395 nm ⁽¹⁰⁾		0.68	2	mW/cm²
ILL_VIS	Illumination wavelengths between 395 nm and 800 nm			29.3	W/cm2
ILL_IR	Illumination wavelength > 800 nm			10	mW/cm²
SOLID STATE ILLUMINATION
ILL_UV	Illumination wavelength < 410 nm ⁽¹⁰⁾			3	mW/cm²
ILL_VIS	Illumination wavelengths between 410 nm and 800 nm			34.7	W/cm2
ILL_IR	Illumination wavelength > 800 nm			10	mW/cm²

(1) Recommended Operating Conditions are applicable after the DMD is installed in the final product.

(2) All power supply connections are required to operate the DMD: V_DD, V_DDA, V_OFFSET, V_BIAS, and V_RESET. All V_SS connections are required to operate the DMD.

(3) All voltage values are with respect to the V_SS ground pins.

(4) V_OFFSETsupply transients must fall within specified max voltages.

(5) To prevent excess current, the supply voltage delta | V_DDA – V_DD | must be less than specified limit.

(6) To prevent excess current, the supply voltage delta | V_BIAS – V_OFFSET | must be less than specified limit.

(7) LVCMOS input pin is DMD_DEN_ARSTZ.

(8) See the low speed interface (LSIF) timing requirements in Timing Requirements.

(9) See the high speed serial interface (HSSI) timing requirements in Timing Requirements.

(10) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination will reduce device lifetime.

(11) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point (TP1) shown in Figure 7-1 and the package thermal resistances using the Micromirror Array Temperature Calculation.

(12) Per Figure 6-1, the maximum operational array temperature should be de-rated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Micromirror Landed Duty Cycle for a definition of micromirror landed duty cycle.

(13) Long-term is defined as the usable life of the device.

(14) Short-term is the total cumulative time over the useful life of the device.

(15) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(16) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CT_ELR.

(17) The active area of the DMD is surrounded by an aperture on the inside of the DMD window surface that masks structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light illuminating the area outside the active array can scatter and create adverse effects to the performance of an end application using the DMD. The illumination optical system should be designed to minimize light flux incident outside the active array. Depending on the particular system's optical architecture and assembly tolerances, the amount of overfill light on the outside of the active array may cause system performance degradation.

(18) Applies to the region in red in Figure 6-2.