JAJSLH9A March 2021 – May 2022 DLP650TE
PRODUCTION DATA
SYMBOL | PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|---|
tpd | Output propagation, clock to Q, rising edge of LS_CLK (differential clock signal) input to LS_RDATA output. (1) | CL = 5 pF | 11.1 | ns | ||
tpd | Output propagation, clock to Q, rising edge of LS_CLK (differential clock signal) input to LS_RDATA output. (1) | CL = 10 pF | 11.3 | ns | ||
Slew rate, LS_RDATA | 20% to 80%, CL <40p | 0.35 | V/ns | |||
Output duty cycle distortion, LS_RDATA_A and LS_RDATA_B | 50 − (C2Q_rise − C2Q_fall )x130e6x100 | 40% | 60% |