JAJSJN6D April   2019  – December 2023 DLP660TE

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
    1. 4.1 Pin Functions—Test Pads
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Capacitance at Recommended Operating Conditions
    8. 5.8  Timing Requirements
    9. 5.9  System Mounting Interface Loads
    10. 5.10 Micromirror Array Physical Characteristics
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Optical Interface and System Image Quality
        1. 6.5.1.1 Numerical Aperture and Stray Light Control
        2. 6.5.1.2 Pupil Match
        3. 6.5.1.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 DMD Die Temperature Sensing
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
      1. 9.2.1 Layers
      2. 9.2.2 Impedance Requirements
      3. 9.2.3 Trace Width, Spacing
        1. 9.2.3.1 Voltage Signals
  11. 10Device and Documentation Support
    1. 10.1 サード・パーティ製品に関する免責事項
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
    4. 10.4 ドキュメントの更新通知を受け取る方法
    5. 10.5 サポート・リソース
    6. 10.6 Trademarks
    7. 10.7 静電気放電に関する注意事項
    8. 10.8 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

GUID-BC8AFC29-FB2A-4ADA-92AA-11561BC44E74-low.gifFigure 4-1 Series 610350-pin FYGBottom View
CAUTION:

For reliable, long-term operation of the 0.66-inch UHD S610 DMD, it is critical to properly manage the layout and operation of the signals identified in the table below. For specific details and guidelines, refer to the PCB Design Requirements for TI DLP Standard TRP Digital Micromirror Devices application report before designing the board.

Table 4-1 Pin Functions
PIN TYPE SIGNAL DATA RATE DESCRIPTION
NAME NO.
DATA INPUTS
D_AN(0) C7 Input 2xLVDS LVDS pair for Data Bus A (15:0)
D_AP(0) C8
D_AN(1) D4
D_AP(1) E4
D_AN(2) C5
D_AP(2) C4
D_AN(3) D6
D_AP(3) C6
D_AN(4) D8
D_AP(4) D7
D_AN(5) D3
D_AP(5) E3
D_AN(6) B3
D_AP(6) C3
D_AN(7) E11
D_AP(7) E10
D_AN(8) E6
D_AP(8) E5
D_AN(9) B10
D_AP(9) C10
D_AN(10) B8
D_AP(10) B9
D_AN(11) C13
D_AP(11) C14
D_AN(12) D15
D_AP(12) E15
D_AN(13) B12
D_AP(13) B13
D_AN(14) B15
D_AP(14) B16
D_AN(15) C16
D_AP(15) C17
D_BN(0) Y8 Input 2xLVDS LVDS pair for Data Bus B (15:0)
D_BP(0) Y7
D_BN(1) X4
D_BP(1) W4
D_BN(2) Z3
D_BP(2) Y3
D_BN(3) X6
D_BP(3) Y6
D_BN(4) X8
D_BP(4) X7
D_BN(5) X3
D_BP(5) W3
D_BN(6) W15
D_BP(6) X15
D_BN(7) W11
D_BP(7) W10
D_BN(8) W6
D_BP(8) W5
D_BN(9) AA9
D_BP(9) AA10
D_BN(10) Z8
D_BP(10) Z9
D_BN(11) Y13
D_BP(11) Y14
D_BN(12) Z10
D_BP(12) Y10
D_BN(13) Z12
D_BP(13) Z13
D_BN(14) Z15
D_BP(14) Z16
D_BN(15) Y16
D_BP(15) Y17
D_CN(0) C18 Input 2xLVDS LVDS pair for Data Bus C (15:0)
D_CP(0) C19
D_CN(1) A20
D_CP(1) A19
D_CN(2) L23
D_CP(2) K23
D_CN(3) C23
D_CP(3) B23
D_CN(4) G23
D_CP(4) H23
D_CN(5) H24
D_CP(5) G24
D_CN(6) B18
D_CP(6) B19
D_CN(7) C21
D_CP(7) B21
D_CN(8) D23
D_CP(8) E23
D_CN(9) D25
D_CP(9) C25
D_CN(10) L24
D_CP(10) K24
D_CN(11) K25
D_CP(11) J25
D_CN(12) B24
D_CP(12) A24
D_CN(13) D26
D_CP(13) C26
D_CN(14) G25
D_CP(14) F25
D_CN(15) K26
D_CP(15) J26
D_DN(0) Y18 Input 2xLVDS LVDS pair for Data Bus D (15:0)
D_DP(0) Y19
D_DN(1) AA20
D_DP(1) AA19
D_DN(2) N23
D_DP(2) P23
D_DN(3) Y23
D_DP(3) Z23
D_DN(4) U23
D_DP(4) T23
D_DN(5) T24
D_DP(5) U24
D_DN(6) Z18
D_DP(6) Z19
D_DN(7) Y21
D_DP(7) Z21
D_DN(8) X23
D_DP(8) W23
D_DN(9) X25
D_DP(9) Y25
D_DN(10) N24
D_DP(10) P24
D_DN(11) P25
D_DP(11) R25
D_DN(12) Z24
D_DP(12) AA24
D_DN(13) X26
D_DP(13) Y26
D_DN(14) U25
D_DP(14) V25
D_DN(15) P26
D_DP(15) R26
DCLK_AN B6 Input LVDS LVDS pair for Data Clock A
DCLK_AP B5
DCLK_BN Z6 Input LVDS LVDS pair for Data Clock B
DCLK_BP Z5
DCLK_CN G26 Input LVDS LVDS pair for Data Clock C
DCLK_CP F26
DCLK_DN U26 Input LVDS LVDS pair for Data Clock D
DCLK_DP V26
DATA CONTROL INPUTS
SCTRL_AN A10 Input LVDS LVDS pair for Serial Control (Sync) A
SCTRL_AP A9
SCTRL_BN Y4 Input LVDS LVDS pair for Serial Control (Sync) B
SCTRL_BP Y5
SCTRL_CN E24 Input LVDS LVDS pair for Serial Control (Sync) C
SCTRL_CP D24
SCTRL_DN W24 Input LVDS LVDS pair for Serial Control (Sync) D
SCTRL_DP X24
DAD CONTROL INPUTS
RESET_ADDR(0) R3 Input LVCMOS Reset Driver Address Select. The bond pad connects to an internal pulldown circuit.
RESET_ADDR(1) R4
RESET_ADDR(2) T3
RESET_ADDR(3) U2
RESET_MODE(0) P4 Input LVCMOS Reset Driver Mode Select. The bond pad connects to an internal pulldown circuit.
RESET_MODE(1) V3
RESET_OEZ R2 Input LVCMOS Active low. Output Enable signal for an internal reset driver circuitry. Bond Pad connects to an internal pullup circuit
RESET_SEL(0) P3 Input LVCMOS Reset Driver Level Select. The bond pad connects to an internal pulldown circuit.
RESET_SEL(1) V2
RESET_STROBE W8 Input LVCMOS Rising edge on RESET_STROBE latches in the control signals. The bond pad connects to an internal pulldown circuit.
RESETZ U4 Input LVCMOS Active low. Places reset circuitry in known VOFFSET state. The bond pad connects to an internal pulldown circuit.
SCP CONTROL
SCPCLK W17 Input LVCMOS Serial communications port clock. SCPCLK is only active when SCPENZ goes low. The bond pad connects to an internal pulldown circuit.
SCPDI W18 Input LVCMOS Serial communications port data. Synchronous to the rising edge of SCPCLK. The bond pad connects to an internal pulldown circuit.
SCPENZ X18 Input LVCMOS Active low serial communications port enable. The bond pad connects to an internal pulldown circuit.
SCPDO W16 Output LVCMOS Serial communications port output
EXTERNAL REGULATOR SIGNALS
EN_BIAS J4 Output LVCMOS Active high. Enable signal for external VBIAS regulator
EN_OFFSET H3 Output LVCMOS Active high. Enable signal for external VOFFSET regulator
EN_RESET J3 Output LVCMOS Active high. Enable signal for external VRESET regulator
OTHER SIGNALS
RESET_IRQZ U3 Output LVCMOS Active low. Output interrupt to DLP controller (ASIC)
TEMP_PLUS E16 Analog Temperature sensor diode anode(1)
TEMP_MINUS E17 Analog Temperature sensor diode cathode (1)
POWER
VBIAS A5, A6, A7 Power Power supply for positive bias level of micromirror reset signal
VCC A8, B2, C1, D1, D10, D12, D19, E1, E19, E20, E21, F1, K1, L1, M1, N1, P1,V1, W1, W19, W20, W21, X1, X10, X12, X19, Y1, Z1, Z2, AA2, AA8, Power Power supply for low voltage CMOS logic. Power supply for normal high voltage at micromirror address electrodes. Power supply for offset level during power down sequence
VCCI A11, A16, A17, A18, A21, A22, A23, AA11, AA16, AA17, AA18, AA21, AA22, AA23, Power Power supply for low voltage CMOS LVDS interface
VOFFSET A3, A4, A25, B26, L26, M26, N26, Z26, AA3, AA4, AA25 Power Power supply for high voltage CMOS logic. Power supply for stepped high voltage at micromirror address electrodes. Power supply for offset level of MBRST(15:0)
VRESET G1, H1, J1, R1, T1, U1 Power Power supply for the negative reset level of the micromirror reset signal
VSS (Ground) B4, B7, B11, B14, B17, B20, B22, B25, C2, C9, C20, C22, C24, D2, D5, D9, D11, D14, D18, D20, D21, D22, E2, E7, E9, E22, E25, E26, F4, F23, F24, H2, H4, H25, H26, J23, J24, K2, L2, L3, L4, L25, M2, M3, M4, M23, M24, M25, N2, N3, N25, P2,R23, R24, T2, T4, T25, T26, V4, V23, V24, W2, W7, W9, W22, W25, W26, X2, X5, X9, X11, X20, X21, X22, Y2, Y9, Y20, Y22, Y24, Z4, Z7, Z11, Z14, Z17, Z20, Z22, Z25 Ground Common return for all power
RESERVED SIGNALS
RESERVED_PFE E18 Ground Connect to ground on the printed circuit board (PCB). The bond pad connects to an internal pulldown circuit.
RESERVED_TM G4 Ground Connect to ground on the printed circuit board (PCB). The bond pad connects to an internal pulldown circuit.
RESERVED_TP0 E8 Input Do not connect on the printed circuit board (PCB).
RESERVED_TP1 J2 Input Do not connect on the printed circuit board (PCB).
RESERVED_TP2 G2 Input Do not connect on the printed circuit board (PCB).
RESERVED_BA N4 Output Do not connect on the printed circuit board (PCB).
RESERVED_BB K4 Output Do not connect on the printed circuit board (PCB).
RESERVED_BC X17 Output Do not connect on the printed circuit board (PCB).
RESERVED_BD D17 Output Do not connect on the printed circuit board (PCB).
(1) Connect VSS for proper DMD operation.