JAJSQ77 april   2023 DLP670RE

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 説明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  System Mounting Interface Loads
    9. 6.9  Micromirror Array Physical Characteristics
    10. 6.10 Micromirror Array Optical Characteristics
    11. 6.11 Window Characteristics
    12. 6.12 Chipset Component Usage Specification
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On or Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On or Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  10. 9 Power Supply Requirements
    1. 9.1 DMD Power Supply Requirements
    2. 9.2 DMD Power Supply Power-Up Procedure
    3. 9.3 DMD Power Supply Power-Down Procedure
  11. 10Device Documentation Support
    1. 10.1 サード・パーティ製品に関する免責事項
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 サポート・リソース
    6. 10.6 Trademarks
    7. 10.7 静電気放電に関する注意事項
    8. 10.8 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Timing Requirements

Over Recommended Operating Conditions (Section 6.4) unless otherwise noted.(5)
DESCRIPTION(1) MIN TYP MAX UNIT
SCP INTERFACE(2)
tr Rise time 20% to 80% reference points 200 ns
tƒ Fall time 80% to 20% reference points 200 ns
LVDS INTERFACE(2)
tr Rise time 20% to 80% 100 400 ps
tƒ Fall time 80% to 20% 100 400 ps
LVDS CLOCKS(3)
tc Cycle time DCLK_A, 50% to 50% 2.5 ns
DCLK_B, 50% to 50% 2.5
tw Pulse duration DCLK_A, 50% to 50% 1.19 1.25 ns
DCLK_B, 50% to 50% 1.19 1.25
LVDS INTERFACE(3)
tsu Setup time D_A(15:0) before rising or falling edge of DCLK_A 0.17 ns
D_B(15:0) before rising or falling edge of DCLK_B 0.17
tsu Setup time SCTRL_A before rising or falling edge of DCLK_A 0.17 ns
SCTRL_B before rising or falling edge of DCLK_B 0.17
th Hold time D_A(15:0) after rising or falling edge of DCLK_A 0.47 ns
D_B(15:0) after rising or falling edge of DCLK_B 0.47
th Hold time SCTRL_A after rising or falling edge of DCLK_A 0.47 ns
SCTRL_B after rising or falling edge of DCLK_B 0.47
LVDS INTERFACE(4)
tskew Skew time Channel B relative to Channel A(4) Channel A includes the following LVDS pairs:
DCLK_AP and DCLK_AN
SCTRL_AP and SCTRL_AN
D_AP(15:0) and D_AN(15:0)		 –1.25 1.25 ns
Channel B includes the following LVDS pairs:
DCLK_BP and DCLK_BN
SCTRL_BP and SCTRL_BN
D_BP(15:0) and D_BN(15:0)
(1) Refer to Section 5 for pin details.
(2) Refer to Figure 6-6.
(3) Refer to Figure 6-8.
(4) Refer to Figure 6-9.
(5) Tested at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be considered.
GUID-AE723F35-2AB9-4188-8C3F-6E15FBE7782B-low.gif
Not to scale
Refer to the SCP Interface section of the Recommended Operating ConditionsSection 6.4.
Figure 6-2 SCP Timing Parameters
GUID-0D2DA0EA-00A6-47E4-B391-A52231941368-low.gif
Refer to the LVDS Interface section of the Recommended Operating Conditions (Section 6.4).
Refer to the Pin Functions table for the list of LVDS pins.
Figure 6-3 LVDS Voltage Definitions (References)
GUID-E86BDCF6-53D1-4058-A5CA-6293D9E1901C-low.gif
Not to scale
Refer to the LVDS Interface section of the Recommended Operating Conditions (Section 6.4).
Figure 6-4 LVDS Voltage Parameters
GUID-D9C1C5B8-BBC9-4309-93A4-088197B9A644-low.gif
Refer to the LVDS Interface section of the Recommended Operating Conditions (Section 6.4).
Refer to the Pin Functions table for the list of LVDS pins.
Figure 6-5 LVDS Equivalent Input Circuit
GUID-9B34FC3E-61BA-4B4B-B21E-E46DB9B41D9A-low.gif
Not to scale
Refer to the timing requirements.
Refer to the Pin Functions table for the list of LVDS pins and SCP pins.
Figure 6-6 Rise Time and Fall Time
GUID-1153600C-B6CF-4E2B-BFDE-C4EC07977CFA-low.gif Figure 6-7 Test Load Circuit for Output Propagation Measurement

For output timing analysis, the tester pin electronics and its transmission line effects must be considered. System design should use IBIS or other simulation tools to correlate the timing reference load to a system environment. See Figure 6-7.

GUID-B6645863-2F12-4B7A-8491-0485D966B45F-low.gif
Not to scale
Refer to the LVDS Interface section in the timing requirements.
Figure 6-8 Timing Requirement Parameter Definitions
GUID-B772ACA4-E4C2-4AB8-BB60-974EE687A6F1-low.gif
Not to scale
Refer to the LVDS Interface section in the timing requirements.
Figure 6-9 LVDS Interface Channel Skew Definition