JAJSQ77 april   2023 DLP670RE

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 説明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  System Mounting Interface Loads
    9. 6.9  Micromirror Array Physical Characteristics
    10. 6.10 Micromirror Array Optical Characteristics
    11. 6.11 Window Characteristics
    12. 6.12 Chipset Component Usage Specification
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On or Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On or Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  10. 9 Power Supply Requirements
    1. 9.1 DMD Power Supply Requirements
    2. 9.2 DMD Power Supply Power-Up Procedure
    3. 9.3 DMD Power Supply Power-Down Procedure
  11. 10Device Documentation Support
    1. 10.1 サード・パーティ製品に関する免責事項
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 サポート・リソース
    6. 10.6 Trademarks
    7. 10.7 静電気放電に関する注意事項
    8. 10.8 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted).
PARAMETERTEST CONDITIONS(1)MINTYPMAXUNIT
VOHHigh-level output voltageVCC = 3 V, IOH = –20 mA2.4V
VOLLow -level output voltageVCC = 3.45 V, IOL = 15 mA0.4V
IIHHigh-level input current(2)(3)VCC = 3.45 V, VI = VCC250µA
IlLLow-level input currentVCC = 3.45 V, VI = 0–250µA
IOZHigh–impedance output currentVCC = 3.45 V10µA
ICC Supply current(4) VCC = 3.45 V 1100 mA
ICCI VCCI = 3.45 V 510
IOFFSET Supply current(5)(6) VOFFSET = 8.75 V 10 25 mA
IBIAS VBIAS = 16.5 V 10 14
IRESET Supply current(6) VRESET = –10.5 V 10 11 mA
ITOTAL Total Sum 1650
CIInput capacitanceƒ = 1 MHz20pF
COOutput capacitanceƒ = 1 MHz15pF
CMReset group capacitance MBRST(14:0)ƒ = 1 MHz

all inputs interconnected,

(1920 x 1200) array 		365430pF
(1) All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.
(2) Applies to LVCMOS input pins only; excludes LVDS pins and MBRST pins.
(3) LVCMOS input pins utilize an internal 18000-Ω passive resistor for pullup and pulldown configurations. Refer to Section 5 to determine pullup or pulldown configuration used.
(4) To prevent excess current, the supply voltage change |VCCI – VCC| must be less than specified limit.
(5) To prevent excess current, the supply voltage change |VBIAS – VOFFSET| must be less than specified limit.
(6) The DLPA4000 PMIC is able to supply enough current to the VOFFSET, VBIAS, and VRESET pins to correctly operate the DLP670RE.