JAJSHI5G august   2012  – april 2023 DLP7000

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Storage Conditions
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  LVDS Timing Requirements
    8. 7.8  LVDS Waveform Requirements
    9. 7.9  Serial Control Bus Timing Requirements
    10. 7.10 Systems Mounting Interface Loads
    11. 7.11 Micromirror Array Physical Characteristics
    12. 7.12 Micromirror Array Optical Characteristics
    13. 7.13 Window Characteristics
    14. 7.14 Chipset Component Usage Specification
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DLPC410 Chipset DMD Features
        1. 8.3.1.1 DLPC410 - Digital Controller for DLP Discovery 4100 Chipset
        2. 8.3.1.2 DLPA200 - DMD Micromirror Driver
        3. 8.3.1.3 DLPR410 - PROM for DLP Discovery 4100 Chipset
        4. 8.3.1.4 DLP7000 - DLP 0.7 XGA 2xLVDS Type-A DMD
          1. 8.3.1.4.1 DLP7000 XGA Chip Set Interfaces
            1. 8.3.1.4.1.1 DLPC410 Interface Description
              1. 8.3.1.4.1.1.1 DLPC410 IO
              2. 8.3.1.4.1.1.2 Initialization
              3. 8.3.1.4.1.1.3 DMD Device Detection
              4. 8.3.1.4.1.1.4 Power Down
          2. 8.3.1.4.2 DLPC410 to DMD Interface
            1. 8.3.1.4.2.1 DLPC410 to DMD IO Description
            2. 8.3.1.4.2.2 Data Flow
          3. 8.3.1.4.3 DLPC410 to DLPA200 Interface
            1. 8.3.1.4.3.1 DLPA200 Operation
            2. 8.3.1.4.3.2 DLPC410 to DLPA200 IO Description
          4. 8.3.1.4.4 DLPA200 to DLP7000 Interface
            1. 8.3.1.4.4.1 DLPA200 to DLP7000 Interface Overview
        5. 8.3.1.5 Measurement Conditions
    4. 8.4 Device Functional Modes
      1. 8.4.1 DMD Operation
        1. 8.4.1.1 Single Block Mode
        2. 8.4.1.2 Dual Block Mode
        3. 8.4.1.3 Quad Block Mode
        4. 8.4.1.4 Global Mode
    5. 8.5 Optical Interface and System Image Quality Considerations
      1. 8.5.1 Optical Interface and System Image Quality
      2. 8.5.2 Numerical Aperture and Stray Light Control
      3. 8.5.3 Pupil Match
      4. 8.5.4 Illumination Overfill
    6. 8.6 Micromirror Array Temperature Calculation
      1. 8.6.1 Package Thermal Resistance
      2. 8.6.2 Case Temperature
      3. 8.6.3 Micromirror Array Temperature Calculation - Lumens Based (typically used for display applications)
      4. 8.6.4 Micromirror Array Temperature Calculation - Power Density Based
      5. 8.6.5 62
    7. 8.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 8.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 8.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 8.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 8.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Device Description
      3. 9.2.3 Detailed Design Procedure
  10. 10Power Supply Recommendations
    1. 10.1 DMD Power-Up and Power-Down Procedures
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Impedance Requirements
      2. 11.1.2 PCB Signal Routing
      3. 11.1.3 DMD Interface
        1. 11.1.3.1 Trace Length Matching
      4. 11.1.4 DLP7000 Decoupling
        1. 11.1.4.1 Decoupling Capacitors
      5. 11.1.5 VCC and VCC2
      6. 11.1.6 DMD Layout
      7. 11.1.7 DLPA200
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1  Device Support
      1. 12.1.1 Device Marking
    2. 12.2  サード・パーティ製品に関する免責事項
    3. 12.3  Documentation Support
      1. 12.3.1 Related Documents
    4. 12.4  ドキュメントの更新通知を受け取る方法
    5. 12.5  サポート・リソース
    6. 12.6  静電気放電に関する注意事項
    7. 12.7  Export Control Notice
    8. 12.8  用語集
    9. 12.9  Related Links
    10. 12.10 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-E8391B0E-DC2A-48BB-88FB-79876D4FCC47-low.gif Figure 6-1 FLP Package203-Pin CLGABottom View
Table 6-1 Pin Functions
PIN(1) TYPE
(I/O/P)		 SIGNAL DATA
RATE(2)		 INTERNAL
TERM(3)		 CLOCK DESCRIPTION TRACE
NAME NO.
DATA INPUT
D_AN(0) B10 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A Input data bus A (2x LVDS) 368.72
D_AN(1) A13 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 424.61
D_AN(2) D16 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 433.87
D_AN(3) C17 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 391.39
D_AN(4) B18 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 438.57
D_AN(5) A17 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 391.13
D_AN(6) A25 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 563.26
D_AN(7) D22 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 411.62
D_AN(8) C29 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 595.11
D_AN(9) D28 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 543.07
D_AN(10) E27 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 455.98
D_AN(11) F26 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 359.5
D_AN(12) G29 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 542.67
D_AN(13) H28 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 551.51
D_AN(14) J27 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 528.04
D_AN(15) K26 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 484.38
D_AP(0) B12 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 366.99
D_AP(1) A11 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 417.47
D_AP(2) D14 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A Input data bus A - continued (2x LVDS) 434.89
D_AP(3) C15 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 394.67
D_AP(4) B16 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 437.3
D_AP(5) A19 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 389.01
D_AP(6) A23 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 562.92
D_AP(7) D20 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 410.34
D_AP(8) A29 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 594.61
D_AP(9) B28 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 539.88
D_AP(10) C27 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 456.78
D_AP(11) D26 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 360.68
D_AP(12) F30 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 543.97
D_AP(13) H30 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 570.85
D_AP(14) J29 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 527.18
D_AP(15) K28 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 481.02
D_BN(0) AB10 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B Input data bus B (2x LVDS) 368.72
D_BN(1) AC13 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 424.61
D_BN(2) Y16 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 433.87
D_BN(3) AA17 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 391.39
D_BN(4) AB18 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 438.57
D_BN(5) AC17 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B Input data bus B - continued (2x LVDS) 391.13
D_BN(6) AC25 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 563.26
D_BN(7) Y22 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 411.62
D_BN(8) AA29 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 595.11
D_BN(9) Y28 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 543.07
D_BN(10) W27 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 455.98
D_BN(11) V26 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 360.94
D_BN(12) T30 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 575.85
D_BN(13) R29 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 519.37
D_BN(14) R27 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 532.59
D_BN(15) N27 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 441.14
D_BP(0) AB12 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 366.99
D_BP(1) AC11 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 417.47
D_BP(2) Y14 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 434.89
D_BP(3) AA15 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 394.67
D_BP(4) AB16 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 437.3
D_BP(5) AC19 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 389.01
D_BP(6) AC23 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 562.92
D_BP(7) Y20 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 410.34
D_BP(8) AC29 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B Input data bus B - continued (2x LVDS) 594.61
D_BP(9) AB28 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 539.88
D_BP(10) AA27 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 456.78
D_BP(11) Y26 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 360.68
D_BP(12) U29 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 578.46
D_BP(13) T28 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 509.74
D_BP(14) P28 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 534.59
D_BP(15) P26 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 440
DATA CLOCK
DCLK_AN B22 Input LVCMOS – Differential Terminated - 100 Ω – DCLK for data bus A (2x LVDS) 477.1
DCLK_AP B24 Input LVCMOS – Differential Terminated - 100 Ω – 477.14
DCLK_BN AB22 Input LVCMOS – Differential Terminated - 100 Ω – DCLK for data bus B (2x LVDS) 477.07
DCLK_BP AB24 Input LVCMOS – Differential Terminated - 100 Ω – 477.14
DATA CONTROL INPUTS
SCTRL_AN C21 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A Serial control for data bus A (2x LVDS) 477.07
SCTRL_AP C23 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_A 477.14
SCTRL_BN AA21 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B Serial control for data bus B (2x LVDS) 477.07
SCTRL_BP AA23 Input LVCMOS DDR Differential Terminated - 100 Ω DCLK_B 477.14
SERIAL COMMUNICATION AND CONFIGURATION
SCPCLK E3 Input LVCMOS – Pull-down – Serial port clock 379.29
SCPDO B2 Output LVCMOS – – SCPCLK Serial port output 480.91
SCPDI F4 Input LVCMOS – Pull-down SCPCLK Serial port input 323.56
SCPENZ D4 Input LVCMOS – Pull-down SCPCLK Serial port enable 326.99
PWRDNZ C3 Input LVCMOS – Pull-down – Device Reset 406.28
MODE_A D8 Input LVCMOS – Pull-down – Data bandwidth mode select A 396.05
MODE_B C11 Input LVCMOS – Pull-down – Data bandwidth mode select B 208.86
MICROMIRROR BIAS CLOCKING PULSE
MBRST(0) P2 Input Analog – – – Micromirror Bias Clocking Pulse "MBRST" signals "clock" micromirrors into state of LVCMOS memory cell associated with each mirror.
MBRST(1) AB4 Input Analog – – –
MBRST(2) AA7 Input Analog – – –
MBRST(3) N3 Input Analog – – –
MBRST(4) M4 Input Analog – – –
MBRST(5) AB6 Input Analog – – –
MBRST(6) AA5 Input Analog – – –
MBRST(7) L3 Input Analog – – –
MBRST(8) Y6 Input Analog – – –
MBRST(9) K4 Input Analog – – –
MBRST(10) L5 Input Analog – – –
MBRST(11) AC5 Input Analog – – –
MBRST(12) Y8 Input Analog – – –
MBRST(13) J5 Input Analog – – –
MBRST(14) K6 Input Analog – – –
MBRST(15) AC7 Input Analog – – –
POWER
VCC A7, A15, C1, E1, U1, W1, AB2, AC9, AC15 Power Analog – – – Power for LVCMOS Logic –
VCC1 A21, A27, D30, M30, Y30, AC21, AC27 Power Analog – – – Power supply for LVDS Interface –
VCC2 G1, J1, L1, N1, R1 Power Analog – – – Power for High Voltage CMOS Logic –
VSS A1, A3, A5, A9, B4, B8, B14, B20, B26, B30, C7, C13, C19, C25, D6, D12, D18, D24, E29, F2, F28, G3, G27, H2, H4, H26, J3, J25, K2, K30, L25, L27, L29, M2, M6, M26, M28, N5, N25, N29, P4, P30, R3, R5, R25, T2, T26, U27, V28, V30, W5, W29, Y4, Y12, Y18, Y24, AA3, AA9, AA13, AA19, AA25, AB8, AB14, AB20, AB26, AB30 Power Analog – – – Common return for all power inputs –
RESERVED SIGNALS (NOT FOR USE IN SYSTEM)
RESERVED_AA1 AA1 Input LVCMOS – Pull-down – Pins should be connected to VSS –
RESERVED_B6 B6 Input LVCMOS – Pull-down – – –
RESERVED_T4 T4 Input LVCMOS – Pull-down – – –
RESERVED_U5 U5 Input LVCMOS – Pull-down – – –
NO_CONNECT AA11, AC3, C5, C9, D10, D2, E5, G5, H6, P6, T6, U3, V2, V4, W3, Y10, Y2 – – – – – Do not connect –
(1) The following power supplies are required to operate the DMD: VCC, VCC1, VCC2. VSS must also be connected.
(2) DDR = Double Data Rate. SDR = Single Data Rate. Refer to the LVDS Timing Requirements for specifications and relationships.
(3) Refer to Electrical Characteristics for differential termination specification.