JAJSLA9 データシート

JAJSLA9E may 2015 – april 2023 DLP7000UV

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

FLP|203
- MCLC005B

サーマルパッド・メカニカル・データ

発注情報

jajsla9e_oa

7.6 Electrical Characteristics

over the range of recommended supply voltage and recommended case operating temperature (unless otherwise noted)

PARAMETERS		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OH	High-level output voltage ⁽¹⁾, See Figure 8-4	V_CC = 3.0 V, I_OH = –20 mA	2.4			V
V_OL	Low-level output voltage ⁽¹⁾, See Figure 8-4	V_CC = 3.6 V, I_OH = 15 mA			0.4	V
V_MBRST	Clocking Pulse Waveform applied to MBRST[29:0] Input Pins (supplied by DLPA200)		-27		26.5	V
I_OZ	High impedance output current ⁽¹⁾	V_CC = 3.6 V			10	µA
I_OH	High-level output current⁽¹⁾	V_OH = 2.4 V, V_CC ≥ 3 V			–20	mA
I_OH	High-level output current⁽¹⁾	V_OH = 1.7 V, V_CC ≥ 2.25 V			–15	mA
I_OL	Low-level output current⁽¹⁾	V_OL = 0.4 V, V_CC ≥ 3 V			15	mA
I_OL	Low-level output current⁽¹⁾	V_OL = 0.4 V, V_CC ≥ 2.25 V			14	mA
V_IH	High-level input voltage ⁽¹⁾		1.7	VCC + .3		V
V_IL	Low-level input voltage ⁽¹⁾		–0.3		0.7	V
I_IL	Low-level input current ⁽¹⁾	V_CC = 3.6 V, V_I = 0 V			–60	µA
I_IH	High-level input current ⁽¹⁾	V_CC = 3.6 V, V_I = V_CC			200	µA
I_CC	Current into V_CC pin	V_CC = 3.6 V			1475	mA
I_CCI	Current into V_CCI pin ⁽²⁾	V_CCI = 3.6 V			450	mA
I_CC2	Current into V_CC2 pin	V_CC2 = 8.75 V			25	mA
P_D	Power dissipation			2.0		W
Z_IN	Internal differential impedance		95		105	Ω
Z_LINE	Line differential impedance (PWB, Trace)		90	100	110	Ω
C_I	Input capacitance ⁽¹⁾	f = 1 MHz			10	pF
C_O	Output capacitance ⁽¹⁾	f = 1 MHz			10	pF
C_IM	Input capacitance for MBRST[0:15] pins	f = 1 MHz	220		270	pF

(1) Applies to LVCMOS pins only.

(2) Exceeding the maximum allowable absolute voltage difference between V_CC and V_CCI may result in excess current draw. See Section 7.1 for details.