JAJSP81B October   2022  – September 2023 DLP801XE

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5.     12
    6. 6.5  Thermal Information
    7. 6.6  Electrical Characteristics
    8. 6.7  Timing Requirements
    9.     16
    10. 6.8  System Mounting Interface Loads
    11.     18
    12. 6.9  Micromirror Array Physical Characteristics
    13.     20
    14. 6.10 Micromirror Array Optical Characteristics
    15.     22
    16. 6.11 Window Characteristics
    17. 6.12 Chipset Component Usage Specification
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Power Density Calculation
    8. 7.8 Window Aperture Illumination Overfill Calculation
    9. 7.9 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.9.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.9.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.9.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.9.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Temperature Sensor Diode
  10. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Requirements
    2. 9.2 DMD Power Supply Power-Up Procedure
    3. 9.3 DMD Power Supply Power-Down Procedure
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Layers
      2. 10.2.2 Impedance Requirements
      3. 10.2.3 Trace Width, Spacing
        1. 10.2.3.1 Voltage Signals
  12. 11Device and Documentation Support
    1. 11.1 サード・パーティ製品に関する免責事項
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
    3. 11.3 Device Markings
    4. 11.4 Documentation Support
      1. 11.4.1 Related Documentation
    5. 11.5 ドキュメントの更新通知を受け取る方法
    6. 11.6 サポート・リソース
    7. 11.7 Trademarks
    8. 11.8 静電気放電に関する注意事項
    9. 11.9 用語集
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power Supply Information
IDD Supply current VDD(1) 1200 mA
IDDI Supply current VDDI(1) 340 mA
ICC2 Supply current VCC2 40 mA
PDD Supply power VDD(1) 2340 mW
PDDI Supply power VDDI(1) 663 mW
PCC2 Supply power VCC2 420 mW
LVCMOS
VOH High-level output voltage IOH = 2 mA 0.8 × VDD
VOL Low-level output voltage IOL = 2 mA 0.2 × VDD
IOZ High impedance output current VDD = 1.95 V 10 µA
IIL Low-level input current VDD= 1.95 V, Vin = 0 V –60 µA
IIH High-level input current(2) VDD = 1.95 V, Vin =  VDD 200 µA
Capacitances
CI Input capacitance: LVDS pins f = 1 MHz 20 pF
CI Input capacitance(2) f = 1 MHz 15 pF
CO Output capacitance(2) f = 1 MHz 15 pF
CIM Input capacitance for MBRST[0:14] pins f = 75  kHz 400 450 570 pF
(1) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than the specified limit in Absolute Maximum Ratings.
(2) Applies to LVCMOS pins only. Excludes LVDS pins and test pad pins