JAJSP81 データシート

JAJSP81B October 2022 – September 2023 DLP801XE

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

FYV|350
- MCCC010

サーマルパッド・メカニカル・データ

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is implied when operating the device above or below these limits.

		MIN	NOM	MAX	UNIT
VOLTAGE SUPPLY
V_DD	Supply voltage for LVCMOS core logic⁽¹⁾	1.65	1.8	1.95	V
V_DDI	Supply voltage for LVDS Interface⁽¹⁾	1.65	1.8	1.95	V
V_CC2	Micromirror Electrode and HVCMOS voltage⁽¹⁾⁽²⁾	9.5	10	10.5	V
V_MBRST	Micromirror Bias / Reset Voltage⁽¹⁾	–17		21.5	V
\|V_DD – V_DDI\|	Supply voltage delta (absolute value)⁽³⁾		0	0.3	V
LVCMOS
V_IH(DC)	Input High Voltage	0.7 × VDD		V_DD + 0.3	V
V_IL(DC)	Input Low Voltage	–0.3		0.3 × VDD	V
V_IH(AC)	Input High Voltage	0.8 × VDD		V_DD + 0.3	V
V_IL(AC)	Input Low Voltage	–0.3		0.2 × VDD	V
I_OH	High-level Output Current			2	mA
I_OL	Low-level Output Current	–2			mA
t_PWRDNZ	PWRDNZ pulse width⁽⁴⁾	10			ns
SCP INTERFACE
F_SCPCLK	SCP clock frequency	50		500	kHz
SCPCLK_DCDIN	SCP Clk Input duty cycle	40%		60%
LVDS INTERFACE
F_CLOCK	Clock frequency for LVDS interface (all channels), DCLK⁽⁵⁾			400	MHz
DCD_IN	Input CLK Duty Cycle Distortion tolerance	44%		56%
\|V_ID\|	Input differential voltage (absolute value)⁽⁶⁾	150	300	440	mV
V_CM	Common mode voltage⁽⁶⁾	1100	1200	1300	mV
V_LVDS	LVDS voltage⁽⁶⁾	880		1520	mV
t_{LVDS_RSTZ}	Time required for LVDS receivers to recover from PWRDNZ	2			µs
Z_IN	Internal differential termination resistance	80	100	120	Ω
Z_LINE	Line differential impedance (PWB/trace)	90	100	110	Ω
ENVIRONMENTAL
T_ARRAY	Array temperature, long-term operational⁽⁸⁾⁽¹⁰⁾⁽¹¹⁾	10		40 to 70⁽¹⁰⁾	°C
T_ARRAY	Array temperature, short-term operational, 500 hr max⁽¹⁰⁾⁽¹³⁾	0		10	°C
T_{DP -AVG}	Average dew point average temperature (non-condensing)⁽¹²⁾			28	°C
T_DP-ELR	Elevated dew point temperature range (non-condensing)⁽¹³⁾	28		36	°C
CT_ELR	Cumulative time in elevated dew point temperature range			24	Months
Q_AP-ILL	Window aperture illumination overfill⁽¹⁴⁾⁽¹⁵⁾⁽¹⁶⁾			17	W/cm²
SOLID STATE ILLUMINATION SINGLE-CHIP ARCHITECTURE
ILL_UV	Illumination power at wavelengths < 410 nm⁽⁷⁾⁽¹⁸⁾			10	mW/cm²
ILL_VIS	Illumination power at wavelengths ≥ 410 nm and ≤ 800 nm⁽¹⁷⁾⁽¹⁸⁾			40	W/cm²
ILL_IR	Ilumination power at wavelengths > 800 nm⁽¹⁸⁾			10	mW/cm²
ILL_BLU	Illumination power at wavelengths ≥ 410 nm and ≤ 475 nm⁽¹⁷⁾⁽¹⁸⁾			12.8	W/cm²
ILL_BLU1	Illumination power at wavelengths ≥ 410 nm and ≤ 440 nm⁽¹⁷⁾⁽¹⁸⁾			2	W/cm²
SOLID STATE ILLUMINATION MULTI-CHIP ARCHITECTURE ⁽¹⁹⁾
ILL_UV	Illumination power at wavelength < 410 nm⁽⁷⁾⁽¹⁸⁾			10	mW/cm²
ILL_VIS	Illumination power at wavelengths ≥ 410 nm and ≤ 800 nm⁽¹⁷⁾⁽¹⁸⁾			40	W/cm²
ILL_IR	Illumination power at wavelength > 800 nm⁽¹⁸⁾			10	mW/cm²
ILL_BLU	Illumination power at wavelengths ≥ 410 nm and ≤ 475 nm⁽¹⁷⁾⁽¹⁸⁾			22	W/cm²
ILL_BLU1	Illumination power at wavelengths ≥ 410 nm and ≤ 440 nm⁽¹⁷⁾⁽¹⁸⁾			2	W/cm²

(1) All voltages are referenced to common ground V_SS. V_DD, V_DDI, and V_CC2 power supplies are all required for proper DMD operation. V_SS must also be connected.

(2) V_CC2 supply transients must fall within specified max voltages.

(3) To prevent excess current, the supply voltage delta |V_DDI – V_DD| must be less than the specified limit. See the DMD Power Supply Requirements.

(4) PWRDNZ input pin resets the SCP and disables the LVDS receivers. The PWRDNZ input pin overrides the SCPENZ input pin and tristates the SCPDO output pin.

(5) See LVDS clock timing requirements in Timing Requirements.

(6) See Figure 6-5 for the LVDS waveform requirements.

(7) Simultaneous exposure of the DMD to the maximum Recommend Operating Conditions for temperature and UV illumination reduces device lifetime.

(8) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1), shown in Figure 7-1 using the Micromirror Array Temperature Calculation.

(9) Long-term is defined as the usable life of the device.

(10) Per Figure 6-1, the maximum operational array temperature is derated based on the micromirror landed duty cycle that the DMD experiences in the end application. See Micromirror Landed-on/Landed-off Duty Cycle for a definition of micromirror landed duty cycle.

(11) Short-term is the total cumulative time over the useful life of the device.

(12) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(13) Exposure to dew point temperatures in the elevated range during storage and operation is limited to less than a total cumulative time of CT_ELR.

(14) Applies to region defined in Figure 6-2

(15) The active area of the DMD is surrounded by an aperture on the inside of the DMD window surface that masks structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light illuminating the area outside the active array can scatter and create adverse effects to the performance of an end application using the DMD. Minimizing the light flux incident outside the active array is a design requirement of the illumination optical system. Depending on the particular optical architecture and assembly tolerances of the optical system, the amount of overfill light on the outside of the active array may cause system performance degradation.

(16) To calculate see Window Aperture Illumination Overfill Calculation.

(17) The maximum allowable optical power incident on the DMD is limited by the maximum optical power density for each wavelength range specified and the micromirror array temperature (T_ARRAY).

(18) To calculate see Micromirror Power Density Calculation.

(19) Multichip architectures must use the same DMD device (DLP801XE) for all DMDs in the product.