JAJSFX3F august 2012 – april 2023 DLP9500
PRODUCTION DATA
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
ƒDCLK_x | DCLK_x clock frequency (where x = [A, B, C, or D]) | 200 | 400 | MHz | |
tc | Clock cycle - DLCK_x | 2.5 | ns | ||
tw | Pulse duration - DLCK_x | 1.25 | ns | ||
ts | Setup time - D_x[15:0] and SCTRL_x before DCLK_x | 0.35 | ns | ||
th | Hold time, D_x[15:0] and SCTRL_x after DCLK_x | 0.35 | ns | ||
tskew | Skew between any two buses (A ,B, C, and D) | –1.25 | 1.25 | ns |