JAJSFX3F
august 2012 – april 2023
DLP9500
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
Storage Conditions
6.3
ESD Ratings
6.4
Recommended Operating Conditions
6.5
Thermal Information
6.6
Electrical Characteristics
6.7
LVDS Timing Requirements
6.8
LVDS Waveform Requirements
6.9
Serial Control Bus Timing Requirements
6.10
Systems Mounting Interface Loads
6.11
Micromirror Array Physical Characteristics
6.12
Micromirror Array Optical Characteristics
6.13
Window Characteristics
6.14
Chipset Component Usage Specification
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
DLPC410 - Digital Controller for DLP Discovery 4100 Chipset
7.3.2
DLPA200 - DMD Micromirror Drivers
7.3.3
DLPR410 - PROM for DLP Discovery 4100 Chipset
7.3.4
DLP9500 - DLP 0.95 1080p 2xLVDS Type-A DMD 1080p DMD
7.3.4.1
DLP9500 1080p Chipset Interfaces
7.3.4.1.1
DLPC410 Interface Description
7.3.4.1.1.1
DLPC410 IO
7.3.4.1.1.2
Initialization
7.3.4.1.1.3
DMD Device Detection
7.3.4.1.1.4
Power Down
7.3.4.1.2
DLPC410 to DMD Interface
7.3.4.1.2.1
DLPC410 to DMD IO Description
7.3.4.1.2.2
Data Flow
7.3.4.1.3
DLPC410 to DLPA200 Interface
7.3.4.1.3.1
DLPA200 Operation
7.3.4.1.3.2
DLPC410 to DLPA200 IO Description
7.3.4.1.4
DLPA200 to DLP9500 Interface
7.3.4.1.4.1
DLPA200 to DLP9500 Interface Overview
7.3.5
Measurement Conditions
7.4
Device Functional Modes
7.4.1
Single Block Mode
7.4.2
Dual Block Mode
7.4.3
Quad Block Mode
7.4.4
Global Block Mode
7.5
Window Characteristics and Optics
7.5.1
Optical Interface and System Image Quality
7.5.2
Numerical Aperture and Stray Light Control
7.5.3
Pupil Match
7.5.4
Illumination Overfill
7.6
Micromirror Array Temperature Calculation
7.6.1
Thermal Test Points
7.6.2
Micromirror Array Temperature Calculation - Lumens Based
7.6.3
Micromirror Array Temperature Calculation - Power Density Based
7.6.4
59
7.7
Micromirror Landed-On and Landed-Off Duty Cycle
7.7.1
Definition of Micromirror Landed-On/Landed-Off Duty Cycle
7.7.2
Landed Duty Cycle and Useful Life of the DMD
7.7.3
Landed Duty Cycle and Operational DMD Temperature
7.7.4
Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.1.1
Device Description
8.2.2
Detailed Design Procedure
9
Power Supply Recommendations
9.1
Power-Up Sequence (Handled by the DLPC410)
9.2
DMD Power-Up and Power-Down Procedures
10
Layout
10.1
Layout Guidelines
10.1.1
Impedance Requirements
10.1.2
PCB Signal Routing
10.1.3
Fiducials
10.1.4
PCB Layout Guidelines
10.1.4.1
DMD Interface
10.1.4.1.1
Trace Length Matching
10.1.4.2
DLP9500 Decoupling
10.1.4.2.1
Decoupling Capacitors
10.1.4.3
VCC and VCC2
10.1.4.4
DMD Layout
10.1.4.5
DLPA200
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.1.1
Device Nomenclature
11.1.2
Device Marking
11.2
Documentation Support
11.2.1
Related Documentation
11.3
Related Links
11.4
サポート・リソース
11.5
Trademarks
11.6
静電気放電に関する注意事項
11.7
用語集
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
FLN|355
MCLG019B
サーマルパッド・メカニカル・データ
発注情報
jajsfx3f_oa
7.3.4.1.1
DLPC410 Interface Description