Optically, the DLP9500 consists of 2,073,600 highly reflective, digitally switchable, micrometer-sized mirrors (micromirrors), organized in a two-dimensional array of 1920 micromirror columns by 1080 micromirror rows. Each aluminum micromirror is approximately 10.8 microns in size (see the Micromirror Pitch in the DMD Micromirror Array and Hinge-Axis Orientation section and is switchable between two discrete angular positions: –12° and 12°. The angular positions are measured relative to a 0° flat state, which is parallel to the array plane (see Micromirror Landed Positions and Light paths section). The tilt direction is perpendicular to the hinge-axis, which is positioned diagonally relative to the overall array. The On State landed position is directed toward row 0, column 0 (upper left) corner of the device package (see the Micromirror Hinge-Axis Orientation in DMD Micromirror Array, Pitch Hinge-Axis Orientation). In the field of visual displays, the 1920 × 1080 pixel resolution is referred to as 1080p.

Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell contents, after the mirror clocking pulse is applied. The angular position (–12° or +12°) of the individual micromirrors changes synchronously with a micromirror clocking pulse, rather than being synchronous with the CMOS memory cell data update. Therefore, writing a logic 1 into a memory cell followed by a mirror clocking pulse will result in the corresponding micromirror switching to a 12° position. Writing a logic 0 into a memory cell followed by a mirror clocking pulse will result in the corresponding micromirror switching to a –12° position.

Updating the angular position of the micromirror array consists of two steps. First, updating the contents of the CMOS memory. Second, application of a micromirror clocking pulse to all or a portion of the micromirror array (depending upon the configuration of the system). Micromirror clocking pulses are generated externally by two DLPA200s, with application of the pulses being coordinated by the DLPC410 controller.

Around the perimeter of the 1920 by 1080 array of micromirrors is a uniform band of border micromirrors. The border micromirrors are not user-addressable. The border micromirrors land in the –12° position once power has been applied to the device. There are 10 border micromirrors on each side of the 1920 by 1080 active array.

Figure 7-1 shows a DLPC410 and DLP9500 chipset block diagram. The DLPC410 and DLPA200s control and coordinate the data loading and micromirror switching for reliable DLP9500 operation. The DLPR410 is the programmed PROM required to properly configure the DLPC410 controller. For more information on the chipset components, see Section 8. For a typical system application using the DLP Discovery 4100 chipset including a DLP9500, see Figure 8-1.