JAJSFX3F august   2012  – april 2023 DLP9500

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  LVDS Timing Requirements
    8. 6.8  LVDS Waveform Requirements
    9. 6.9  Serial Control Bus Timing Requirements
    10. 6.10 Systems Mounting Interface Loads
    11. 6.11 Micromirror Array Physical Characteristics
    12. 6.12 Micromirror Array Optical Characteristics
    13. 6.13 Window Characteristics
    14. 6.14 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DLPC410 - Digital Controller for DLP Discovery 4100 Chipset
      2. 7.3.2 DLPA200 - DMD Micromirror Drivers
      3. 7.3.3 DLPR410 - PROM for DLP Discovery 4100 Chipset
      4. 7.3.4 DLP9500 - DLP 0.95 1080p 2xLVDS Type-A DMD 1080p DMD
        1. 7.3.4.1 DLP9500 1080p Chipset Interfaces
          1. 7.3.4.1.1 DLPC410 Interface Description
            1. 7.3.4.1.1.1 DLPC410 IO
            2. 7.3.4.1.1.2 Initialization
            3. 7.3.4.1.1.3 DMD Device Detection
            4. 7.3.4.1.1.4 Power Down
          2. 7.3.4.1.2 DLPC410 to DMD Interface
            1. 7.3.4.1.2.1 DLPC410 to DMD IO Description
            2. 7.3.4.1.2.2 Data Flow
          3. 7.3.4.1.3 DLPC410 to DLPA200 Interface
            1. 7.3.4.1.3.1 DLPA200 Operation
            2. 7.3.4.1.3.2 DLPC410 to DLPA200 IO Description
          4. 7.3.4.1.4 DLPA200 to DLP9500 Interface
            1. 7.3.4.1.4.1 DLPA200 to DLP9500 Interface Overview
      5. 7.3.5 Measurement Conditions
    4. 7.4 Device Functional Modes
      1. 7.4.1 Single Block Mode
      2. 7.4.2 Dual Block Mode
      3. 7.4.3 Quad Block Mode
      4. 7.4.4 Global Block Mode
    5. 7.5 Window Characteristics and Optics
      1. 7.5.1 Optical Interface and System Image Quality
      2. 7.5.2 Numerical Aperture and Stray Light Control
      3. 7.5.3 Pupil Match
      4. 7.5.4 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
      1. 7.6.1 Thermal Test Points
      2. 7.6.2 Micromirror Array Temperature Calculation - Lumens Based
      3. 7.6.3 Micromirror Array Temperature Calculation - Power Density Based
      4. 7.6.4 59
    7. 7.7 Micromirror Landed-On and Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Device Description
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Sequence (Handled by the DLPC410)
    2. 9.2 DMD Power-Up and Power-Down Procedures
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Impedance Requirements
      2. 10.1.2 PCB Signal Routing
      3. 10.1.3 Fiducials
      4. 10.1.4 PCB Layout Guidelines
        1. 10.1.4.1 DMD Interface
          1. 10.1.4.1.1 Trace Length Matching
        2. 10.1.4.2 DLP9500 Decoupling
          1. 10.1.4.2.1 Decoupling Capacitors
        3. 10.1.4.3 VCC and VCC2
        4. 10.1.4.4 DMD Layout
        5. 10.1.4.5 DLPA200
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Marking
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.1.1 Device Description

The DLP9500 1080p chipset offers developers a convenient way to design a wide variety of industrial, medical, telecom and advanced display applications by delivering maximum flexibility in formatting data, sequencing data, and light patterns.

The DLP9500 1080p chipset includes the following four components: DMD digital controller (DLPC410), EEPROM (DLPR410), DMD micromirror driver (DLPA200), and a DMD (DLP9500).

DLPC410 Digital Controller for DLP Discovery 4100 chipset

  • Provides high speed 2XLVDS data and control interface to the user
  • Drives mirror clocking pulse and timing information to the DLPA200
  • Supports random row addressing
  • Controls illumination

DLPR410 PROM for DLP Discovery 4100 chipset

  • Contains startup configuration information for the DLPC410

DLPA200 DMD Micromirror Driver

  • Generates micromirror clocking pulse control (sometimes referred to as a reset) of 15 banks of DMD mirrors. (Two are required for the DLP9500).

DLP9500 DLP 0.95 1080p 2xLVDS Type-A DMD

  • Steers light in two digital positions (+12° and –12°) using 1920 × 1080 micromirror array of aluminum mirrors.

Table 8-1 DLP DLP9500 Chipset Configurations
QUANTITYTI PARTDESCRIPTION
1DLP9500DLP 0.95 1080p 2xLVDS Type-A DMD
1DLPC410Digital Controller for DLP Discovery 4100 chipset
1DLPR410PROM for DLP Discovery 4100 chipset
2DLPA200DMD Micromirror Driver

Reliable function and operation of DLP9500 1080p chipsets require the components be used in conjunction with each other. This document describes the proper integration and use of the DLP9500 1080p chipset components.

The DLP9500 1080p chipset can be combined with a user programmable application FPGA (not included) to create high performance systems.