DLPS082 February   2017 DLPA100

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1. 3.1 Typical Application Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Storage Conditions
    3. 6.3 ESD Ratings
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power Up Sequencing
      2. 7.3.2  Power Down Sequencing
      3. 7.3.3  Shutdown
        1. 7.3.3.1 Thermal
      4. 7.3.4  System Reset
      5. 7.3.5  Interrupt Logic
      6. 7.3.6  Serial Communications Port
      7. 7.3.7  Switching Regulators
        1. 7.3.7.1 Output Voltage - VOUT
        2. 7.3.7.2 Adjustable Linear Regulator - VLIN1
        3. 7.3.7.3 Adjustable Linear Regulator Control - VLIN2
      8. 7.3.8  Fan Controllers
      9. 7.3.9  Color Wheel Motor Driver
        1. 7.3.9.1 Color Wheel Motor Driver Power Dissipation
      10. 7.3.10 Color Wheel Switching Regulator Supply
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Grounding Guidelines
      1. 10.2.1 Completely Isolated Ground Regions
      2. 10.2.2 Single Isolated Ground Region
      3. 10.2.3 Non-isolated Common Ground Region
    3. 10.3 Thermal Guidelines
    4. 10.4 Motor Control Guidelines
    5. 10.5 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • DLP|48
サーマルパッド・メカニカル・データ

7.3.6 Serial Communications Port

The Serial communications port (SCP) is a full duplex, synchronous, character-oriented byte port that allows exchange of data between the DLP controller (master) and the DLPA100.

Table 1. Serial Communications Port Signal Definitions

SIGNAL I/O FROM/TO TYPE DESCRIPTION
SCPK I SCP bus master to slave LVTTL compatible SCP bus serial transfer clock. The host processor (master) generates this clock.
SCPENZ I SCP bus master to slave LVTTL compatible SCP bus access enable (low true). When high, slave will reset to idle state, and SCPDO output will tri-state. Pulling SCPENZ low initiates a read or write access. SCPENZ must remain low for an entire read/write access, and must be pulled high after the last data cycle. To abort a read or write cycle, pull SCPENZ high at any point.
SCPDI I SCP bus master to slave LVTTL compatible SCP bus serial data input. Data bits are valid and must be clocked in on the falling edge of SCPCK.
SCPDO O SCP bus slave to master LVTTL open drain w/tri-state SCP bus serial data output. Data bits must clocked out on the rising edge of SCPCK.

Table 2. Serial Interface Timing Requirements

SYMBOL CHARACTERISTICS TEST CONDITIONS MIN NOM MAX UNIT
A Setup CSZ low to CLK Reference to rising edge of CLK 360 ns
B Byte to Byte Delay Nominally 1 CLK cycle rising edge to rising edge 1.9 µs
C Setup DIN to CSZ High Last byte to slave disable 360 ns
CLK Frequency 0 526 kHz
D CLK Period 1.9 2 µs
E CLK High or Low Time 300 ns
F DIN Set-Up Time Reference to falling edge of CLK 300 ns
G DIN Hold Time Reference from falling edge of CLK 300 ns
H DOUT Propogation Delay Reference from rising edge of CLK 300 ns
CLK Filter (pulse reject) 200 ns
DLPA100 DLPA100_serial_timing.jpgFigure 3. Serial Communications Port Timing Diagram