JAJSGQ4G april   2010  – june 2023 DLPA200

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Configurations Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics Control Logic
    6. 7.6  5-V Linear Regulator
    7. 7.7  Bias Voltage Boost Converter
    8. 7.8  Reset Voltage Buck-Boost Converter
    9. 7.9  VOFFSET/DMDVCC2 Regulator
    10. 7.10 Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 5-V Linear Regulator
      2. 8.3.2 Bias Voltage Boost Converter
      3. 8.3.3 Reset Voltage Buck-Boost Converter
      4. 8.3.4 VOFFSET/DMDVCC2 Regulator
      5. 8.3.5 Serial Communications Port (SCP)
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Component Selection Guidelines
  11. 10Power Supply Recommendations
    1. 10.1 Power Supply Rail Guidelines
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Grounding Guidelines
    2. 11.2 Thermal Considerations
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.4 VOFFSET/DMDVCC2 Regulator

The VOFFSET/DMDVCC2 regulator supplies the internal VOFFSET voltage for the high voltage FET switches and the external DMDVCC2 for the DMD. The VOFFSET voltage level can be different for different generations of DMDs. The VOFFSET voltage level is configured by the DLP Controller chip over the Serial Communication Port. Four control bits select the voltage level while a fifth bit is the on/off control. The module provides 2 status bits to indicate latched and unlatched status bits for under-voltage (VUV) and current-limit (CL) conditions.

Figure 8-4 shows the block diagram of this module. The input decoupling capacitors are shared with other DLPA200 modules. See Section 9.1.1 for recommended component values.

GUID-3BF2990C-055F-4BAB-934E-C0D2BE3AE2DE-low.gifFigure 8-4 Offset Voltage Boost Convertor Block Diagram