JAJSMK8A october   2021  – june 2023 DLPA300

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics Control Logic
    6. 6.6  5-V Linear Regulator
    7. 6.7  Bias Voltage Boost Converter
    8. 6.8  Reset Voltage Buck-Boost Converter
    9. 6.9  VOFFSET Regulator
    10. 6.10 Switching Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 5-V Linear Regulator
      2. 7.3.2 Bias Voltage Boost Converter
      3. 7.3.3 Reset Voltage Buck-Boost Converter
      4. 7.3.4 VOFFSET Regulator
      5. 7.3.5 Serial Communications Port (SCP)
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Component Selection Guidelines
      3. 8.2.3 Application Curves
  10. Power Supply Recommendations
    1. 9.1 Power Supply Rail Guidelines
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Grounding Guidelines
    2. 10.2 Thermal Considerations
  12. 11Device and Documentation Support
    1. 11.1 サード・パーティ製品に関する免責事項
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SERIAL COMMUNICATION PORT INTERFACE
A(1)Setup SCPEN low to SCPCKReference to rising edge of SCPCK360ns
B(1)Byte to byte delayNominally 1 SCPCK cycle, rising edge to rising edge1.9µs
C(1)Setup SCPDI to SCPEN highLast byte to secondary disable360ns
D(1)SCPCK frequency(2)0526kHz
SCPCK period1.92µs
E(1)SCPCK high or low time300ns
F(1)SCPDI set-up timeReference to falling edge of SCPCK300ns
G(1)SCPDI hold timeReference from falling edge of SCPCK300ns
H(1)SCPDO propagation delayReference from rising edge of SCPCK300ns
SCPEN, SCPCK, SCPDI, RESET filter (pulse reject)150ns
OUTPUT MICROMIRROR CLOCKING PULSES
FPREPPhased reset repetition frequency each output pin (non-overlapping)50kHz
FGREPGlobal reset repetition frequency all output pins50kHz
IRLKVRESET output leakage currentOE = 1, VRESET_RAIL = -28.5V-1-10µA
IBLKVBIAS output leakage currentOE = 1, VBIAS_RAIL = 28.5V110µA
IOLKVOFFSET output leakage currentOE = 1, VOFFSET_RAIL = 10.25V110µA
OUTPUT MICROMIRROR CLOCKING PULSE CONTROLS
tSPWSTROBE pulse width10ns
tSPSTROBE period20ns
tOHZOutput time to high impedanceOE Pin = High100ns
tOENOutput enable time from high impedanceOE Pin = Low100ns
tSUSSet-up timeFrom A[3:0], MODE[1:0], and SEL[1:0] to STROBE edge8ns
tHOSHold timeFrom A[3:0], MODE[1:0], and SEL[1:0] to STROBE edge8ns
tPBRPropagation timeFrom STROBE to VBIAS/VRESET edge 50% point.80200ns
tPROFrom STROBE to VRESET/VOFFSET edge 50% point.80200ns
tPOBFrom STROBE to VOFFSET/VBIAS edge 50% point.80200ns
tDELEdge-to-edge propagation deltaMaximum difference between the slowest and fastest propagation times for any given reset output.40ns
tCHCHOutput channel-to-channel propagation deltaMaximum difference between the slowest and fastest propagation times for any two outputs for any given edge.20ns
See Figure 6-1
There is no minimum speed for the serial port. It can be written to statically for diagnostic purposes.
GUID-CABB023A-1DDC-427C-A583-47B5DA076723-low.gifFigure 6-1 Serial Interface Timing