JAJSMK8A october   2021  – june 2023 DLPA300

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics Control Logic
    6. 6.6  5-V Linear Regulator
    7. 6.7  Bias Voltage Boost Converter
    8. 6.8  Reset Voltage Buck-Boost Converter
    9. 6.9  VOFFSET Regulator
    10. 6.10 Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 5-V Linear Regulator
      2. 7.3.2 Bias Voltage Boost Converter
      3. 7.3.3 Reset Voltage Buck-Boost Converter
      4. 7.3.4 VOFFSET Regulator
      5. 7.3.5 Serial Communications Port (SCP)
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Component Selection Guidelines
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
    1. 9.1 Power Supply Rail Guidelines
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Grounding Guidelines
    2. 10.2 Thermal Considerations
  12. 11Device and Documentation Support
    1. 11.1 サード・パーティ製品に関する免責事項
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2 Detailed Design Procedure

The DLPC4430 or DLPC4420 display controller configures the VBIAS and VOFFSET voltage regulators in the DLPA300 micromirror driver through the SCP bus. VBIAS is then used to generate the enable signal for the VRESET external voltage regulator, LM43601 step-down voltage converter. When the VBIAS is enabled, it turns on the two-transistor buffer amplifier. The 2N7002 and BSS84-7-F FETs isolate VBIAS from the VRESET_RAIL and shift the voltage reference to VRESET_RAIL.

The thermal pad on the DLPA300 micromirror controller and the LM43601 step-down voltage converter are electrically connected to the VRESET_RAIL. Furthermore, the AGND and PGND pins on the LM43601 step-down voltage converter are also connected to the VRESET_RAIL. Therefore, the logic levels and analog voltage levels for LM43601 step-down voltage converter are referenced to the –16.5-V VRESET_RAIL.

The LM43601 data sheet provides details for the component selection for the components in the voltage regulator circuit connected to the VRESET_RAIL. The output of the regulator is set to the VRESET value of –16.5 V. The selection of the resistors in the resistor divider sets the output voltages, 6.49 kΩ and 100 kΩ.

The DLP780NE power sequencing requires that the VCC2 power supply ramps up after the 1.8-V supply is powered on and stable, and VOFFSET is powered up and stable. The two conditions are met by the wired-or of the ERROR signal from the LP38513-1.8 ultra-low dropout linear regulator and an enable signal generated from VOFFSET. The 2N7002 enhancement mode FET acts as an inverter and level shifter from VOFFSET to a 3.3-V logic level.

In the event of a power supply failure (such as a pull-the-plug event), VCC2 must be driven low before the 1.8-V supply starts to drop voltage. To achieve this, the TPS3847 12-V voltage monitor triggers a shunt-to-ground power FET to pull VCC2 to ground.