JAJSMK8A october   2021  – june 2023 DLPA300

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics Control Logic
    6. 6.6  5-V Linear Regulator
    7. 6.7  Bias Voltage Boost Converter
    8. 6.8  Reset Voltage Buck-Boost Converter
    9. 6.9  VOFFSET Regulator
    10. 6.10 Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 5-V Linear Regulator
      2. 7.3.2 Bias Voltage Boost Converter
      3. 7.3.3 Reset Voltage Buck-Boost Converter
      4. 7.3.4 VOFFSET Regulator
      5. 7.3.5 Serial Communications Port (SCP)
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Component Selection Guidelines
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
    1. 9.1 Power Supply Rail Guidelines
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Grounding Guidelines
    2. 10.2 Thermal Considerations
  12. 11Device and Documentation Support
    1. 11.1 サード・パーティ製品に関する免責事項
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Bias Voltage Boost Converter

TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IRL Output current: reset outputs Load = 400pF, 39 Ω,
repetition frequency = 50 kHz		 0 18 mA
IQL Output current: quiescent / drivers Load = 400 pF, 39 Ω,
repetition frequency = 50 kHz		 3 mA
IDL Output current: DMD load 0 5 mA
ICLFB Current limit flag Corresponding current on output at P12V = 10.8 V 30 mA
ICLB Current limit Measured on input 330 376 460 mA
VBIAS Output voltage 20.5 21 21.5 V
VUVB VBIAS undervoltage threshold Bias voltage falling 50 92 %VBIAS
VUVLHI VBIAS_LHI undervoltage threshold VBIAS_LHI voltage increasing 8 V
VBIAS_LHI voltage falling 6.5 V
RDS Boost switch RDS(on) TJ = 25°C 2 Ω
VRIP Output ripple voltage(1) 200 mVpk-pk
FSW Switching frequency 1.1 1.3 1.5 MHz
VOSB Voltage overshoot at start up 2 %VBIAS
tss Power up COUT = 3.3 µF, Measured between 10 to 90% of target VBIAS 1 ms
tdis Discharge current sink 400 mA
(1) Output ripple voltage relies on suitable external components being selected and good printed circuit board layout practice.