JAJSNS3A October   2015  – February 2023 DLPA3005

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Parameters
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Description
    3. 7.3 Feature Description
      1. 7.3.1 Supply and Monitoring
        1. 7.3.1.1 Supply
        2. 7.3.1.2 Monitoring
          1. 7.3.1.2.1 Block Faults
          2. 7.3.1.2.2 Auto LED Turn Off Functionality
          3. 7.3.1.2.3 Thermal Protection
      2. 7.3.2 Illumination
        1. 7.3.2.1 Programmable Gain Block
        2. 7.3.2.2 LDO Illumination
        3. 7.3.2.3 Illumination Driver A
        4. 7.3.2.4 RGB Strobe Decoder
          1. 7.3.2.4.1 Break Before Make (BBM)
          2. 7.3.2.4.2 Openloop Voltage
          3. 7.3.2.4.3 Transient Current Limit
        5. 7.3.2.5 Illumination Monitoring
          1. 7.3.2.5.1 Power Good
          2. 7.3.2.5.2 Ratio Metric Overvoltage Protection
        6. 7.3.2.6 Illumination Driver plus Power FETs Efficiency
      3. 7.3.3 External Power FET Selection
        1. 7.3.3.1 Threshold Voltage
        2. 7.3.3.2 Gate Charge and Gate Timing
        3. 7.3.3.3 RDS(ON)
      4. 7.3.4 DMD Supplies
        1. 7.3.4.1 LDO DMD
        2. 7.3.4.2 DMD HV Regulator
        3. 7.3.4.3 DMD/DLPC Buck Converters
        4. 7.3.4.4 DMD Monitoring
          1. 7.3.4.4.1 Power Good
          2. 7.3.4.4.2 Overvoltage Fault
      5. 7.3.5 Buck Converters
        1. 7.3.5.1 LDO Bucks
        2. 7.3.5.2 General Purpose Buck Converter
        3. 7.3.5.3 Buck Converter Monitoring
          1. 7.3.5.3.1 Power Good
          2. 7.3.5.3.2 Overvoltage Fault
        4. 7.3.5.4 Buck Converter Efficiency
      6. 7.3.6 Auxiliary LDOs
      7. 7.3.7 Measurement System
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 SPI
      2. 7.5.2 Interrupt
      3. 7.5.3 Fast-Shutdown in Case of Fault
      4. 7.5.4 Protected Registers
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Component Selection for General-Purpose Buck Converters
      3. 8.2.3 Application Curve
    3. 8.3 System Example With DLPA3005 Internal Block Diagram
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up and Power-Down Timing
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 SPI Connections
      2. 10.1.2 RLIM Routing
      3. 10.1.3 LED Connection
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 サード・パーティ製品に関する免責事項
    3. 11.3 Related Links
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 用語集
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Over operating free-air temperature range. VIN = 12 V, TA = 0 to +70°C, typical values are at TA = 25°C, Configuration according to Section 8.2 (VIN =12 V, IOUT = 16 A, LED, external FETs) (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLIES
INPUT VOLTAGE
VIN Input voltage range VINA – pin 6(6) 12 20 V
VUVLO(7) UVLO threshold VINA falling (through a 5-bit trim function, 0.5-V steps) 3.9 6.22 18.4 V
Hysteresis VINA rising 90 mV
VSTARTUP Startup voltage DMD_VBIAS, DMD_VOFFSET, DMD_VRESET loaded with 10 mA 6 V
INPUT CURRENT
IIDLE Idle current IDLE mode, all VIN pins combined 15 µA
ISTD Standby current STANDBY mode, analog, internal supplies and LDOs enabled, DMD, ILLUMINATION and BUCK CONVERTERS disabled. 3.7 mA
IQ_DMD Quiescent current (DMD) Quiescent current DMD block (in addition to ISTD), VINA + DRST_VIN 0.49 mA
IQ_ILLUM Quiescent current (ILLUM) Quiescent current ILLUM block (in addition to ISTD), V_openloop= 3 V (ILLUM_OLV_SEL), VINA + ILLUM_VIN + ILLUM_A_VIN + ILLUM_B_VIN 21 mA
IQ_BUCK Quiescent current
(per BUCK)		 Quiescent current per BUCK converter (in addition to ISTD), Normal mode, VINA + PWR_VIN + PWR1,2,5,6,7_VIN, PWR1,2,5,6,7_VOUT = 1 V 4.3 mA
Quiescent current per BUCK converter (in addition to ISTD), Normal mode, VINA + PWR_VIN + PWR1,2,5,6,7_VIN, PWR1,2,5,6,7_VOUT = 5 V 15
Quiescent current per BUCK converter (in addition to ISTD), Cycle-skipping mode, VINA + PWR_VIN + PWR1,2,5,6,7_VIN = 1 V 0.41
Quiescent current per BUCK converter (in addition to ISTD), Cycle-skipping mode, VINA + PWR_VIN + PWR1,2,5,6,7_VIN = 5 V 0.46
IQ_TOTAL Quiescent current (Total) Typical Application: ACTIVE mode, all VIN pins combined, DMD, ILLUMINATION and PWR1,2 enabled, PWR3,4,5,6,7 disabled. 38 mA
INTERNAL SUPPLIES
VSUP_5P0V Internal supply, analog 5 V
VSUP_2P5V Internal supply, logic 2.5 V
DMD—LDO DMD
VDRST_VIN 6 12 20 V
VDRST_5P5V 5.5 V
PGOOD Power good DRST_5P5V Rising 80%
Falling 60%
OVP Overvoltage protection DRST_5P5V 7.2 V
Regulator dropout At 25 mA, VDRST_VIN= 5.5 V 56 mV
Regulator current limit(2) 300 340 400 mA
DMD—REGULATOR
RDS(ON) MOSFET ON-resistance Switch A (from DRST_5P5V to DRST_HS_IND) 920 mΩ
Switch B (from DRST_LS_IND to DRST_PGND) 450
VFW Forward voltage drop Switch C (from DRST_LS_IND to DRST_VBIAS(1)), VDRST_LS_IND = 2 V, IF = 100 mA 1.21 V
Switch D (from DRST_LS_IND to DRST_VOFFSET(1)), VDRST_LS_IND = 2 V, IF = 100 mA 1.22
tDIS Rail Discharge time COUT = 1 µF 40 µs
tPG Power-good timeout Not tested in production 15 ms
ILIMIT Switch current limit 610 mA
VOFFSET REGULATOR
VOFFSET Output voltage 10 V
DC output voltage accuracy IOUT = 10 mA -0.3 0.3 V
DC Load regulation IOUT = 0 mA to 10 mA –10 V/A
DC Line regulation IOUT = 10 mA, DRST_VIN = 8 V to 20 V –5 mV/V
VRIPPLE Output ripple IOUT = 10 mA, COUT= 1 µF 200 mVpp
IOUT Output current 0.1 10 mA
PGOOD Power-good threshold (fraction of nominal output voltage) VOFFSET rising 86%
VOFFSET falling 66%
C Output capacitor Recommended value(5) (use same value as output capacitor on VRESET) 1 µF
tDISCHARGE <40 µs at VIN = 8 V 1
VBIAS REGULATOR
VBIAS Output voltage 18 V
DC output voltage accuracy IOUT = 10 mA –0.3 0.3 V
DC Load regulation IOUT = 0 to 10 mA –18 V/A
DC Line regulation IOUT = 10 mA, DRST_VIN = 8 V to 20 V –3 mV/V
VRIPPLE Output ripple IOUT = 10 mA, COUT= 470 nF 200 mVpp
IOUT Output current 0.1 10 mA
PGOOD Power-good threshold (fraction of nominal output voltage) VBIAS rising 86%
VBIAS falling 66%
C Output capacitor Recommended value(5) (use same or smaller value as output capacitors VOFFSET / VRESET) 470 nF
tDISCHARGE <40 µs at VIN = 8 V 470
VRESET REGULATOR
VRST Output voltage –14 V
DC output voltage accuracy IOUT = 10 mA -0.3 0.3 V
DC Load regulation IOUT = 0 to 10 mA –4 V/A
DC Line regulation IOUT = 10 mA, DRST_VIN = 8 to 20 V –2 mV/V
VRIPPLE Output ripple IOUT = 10 mA, COUT = 1 µF 120 mVpp
IOUT Output current 0.1 10 mA
PGOOD Power-good threshold 90%
C Output capacitor Recommended value(5) (use same value as output capacitor on VOFFSET) 1 µF
tDISCHARGE <40 µs at VIN = 8 V 1
DMD - BUCK CONVERTERS
OUTPUT VOLTAGE
VPWR_1_VOUT Output Voltage 1.1 V
VPWR_2_VOUT Output Voltage 1.8 V
DC output voltage accuracy IOUT= 0 mA –3% 3%
MOSFET
RON,H High side switch resistance 25°C, VPWR_1,2_Boost – VPWR1,2_SWITCH = 5.5 V 150 mΩ
RON,L Low side switch resistance(2) 25°C 85 mΩ
LOAD CURRENT
Allowed Load Current(3). 3 A
IOCL Current limit(2) LOUT= 3.3 μH 3.2 3.6 4.2 A
ON-TIME TIMER CONTROL
tON On time VIN = 12 V, VO = 5 V 120 ns
tOFF(MIN) Minimum off time(2) TA = 25°C, VFB = 0 V 270 ns
START-UP
Soft start 1 2.5 4 ms
PGOOD
RatioOV Overvoltage protection 120%
RatioPG Relative power good level Low to high 72%
ILLUMINATION—LDO ILLUM
VILLUM_VIN 6 12 20 V
VILLUM_5P5V 5.5 V
PGOOD Power good ILLUM_5P5V Rising 80%
Falling 60%
OVP Overvoltage protection ILLUM_5P5V 7.2 V
Regulator dropout At 25 mA, VILLUM_VIN = 5.5 V 53 mV
Regulator current limit(2) 300 340 400 mA
ILLUMINATION—DRIVER A,B
VILLUM_A,B_IN Input supply voltage range 6 12 20 V
PWM
ƒSW Oscillator frequency 3 V < VIN < 20 V 600 kHz
tDEAD Output driver dead time HDRV off to LDRV on, TRDLY = 0 28 ns
HDRV off to LDRV on, TRDLY = 1 40
LDRV off to HDRV on, TRDLY = 0 35
OUTPUT DRIVERS
RHDHI High-side driver pull-up resistance VILLUM_A,B_BOOT – VILLUM_A,B_SW = 5 V, IHDRV = –100 mA 4.9 Ω
RHDLO High-side driver pull-down resistance VILLUM_A,B_BOOT – VILLUM_A,B_SW = 5 V, IHDRV = 100 mA 3 Ω
RLDHI Low-side driver pull-up resistance ILDRV = –100 mA 3.1 Ω
RLDLO Low-side driver pull-down resistance ILDRV = 100 mA 2.4 Ω
tHRISE High-side driver rise time(2) CLOAD = 5 nF 23 ns
tHFALL High-side driver fall time(2) CLOAD = 5 nF 19 ns
tLRISE Low-side driver rise time(2) CLOAD = 5 nF 23 ns
tLFALL Low-side driver fall time(2) CLOAD = 5 nF 17 ns
OVERCURRENT PROTECTION
HSD OC High-Side Drive Over Current threshold External switches, VDS threshold(2) 185 mV
BOOT DIODE
VDFWD Bootstrap diode forward voltage IBOOT = 5 mA 0.75 V
PGOOD
RatioUV Undervoltage protection 89%
DRIVERS EXTERNAL RGB STROBE CONTROLLER SWITCHES
CHx_GATE_CNTR_HIGH Gate control high level ILLUM_SW_ILIM_EN[2:0] = 7, register 0x02, ISINK= 400 µA 4.35 V
ILLUM_SW_ILIM_EN[2:0] = 0, register 0x02, ISINK= 400 µA 5.25
CHx_GATE_CNTR_LOW Gate control low level ILLUM_SW_ILIM_EN[2:0] = 7, register 0x02, ISINK= 400 µA 55 mV
ILLUM_SW_ILIM_EN[2:0] = 0, register 0x02, ISINK= 400 µA 55
LED CURRENT CONTROL
VLED_ANODE LED Anode voltage(2) Ratio with respect to VILLUM_A,B_VIN
(Duty cycle limitation).		 0.85x
15.5 V
ILED LED currents VILLUM_A,B_VIN ≥ 8 V. See register SWx_IDAC[9:0] for settings. 1 16(9) A
DC current offset, CH1,2,3_SWITCH RLIM = 12.5 mΩ –150 0 150 mA
Transient LED current limit range (programmable) 20% higher than ILED. Min-setting,
RLIM= 12.5 mΩ		 11%
20% higher than ILED. Max-setting,
RLIM= 12.5 mΩ. Percentage of max current		 133%
tRISE Current rise time ILED from 5% to 95%, ILED = 600 mA, transient current limit disabled(2) 50 µs
BUCK CONVERTERS—LDO_BUCKS
VPWR_VIN Input voltage range PWR1,2,5,6,7_VIN 6 12 20 V
VPWR_5P5V PWR_5P5V 5.5 V
PGOOD Power good PWR_5P5V Rising 80%
Falling 60%
OVP Overvoltage Protection PWR_5P5V 7.2 V
Regulator dropout At 25 mA, VPWR_VIN= 5.5 V 41 mV
Regulator current limit(2) 300 340 400 mA
BUCK CONVERTER - GENERAL PURPOSE BUCK CONVERTER (8)
OUTPUT VOLTAGE
VPWR_6_VOUT Output Voltage (General Purpose Buck2) 8-bit programmable 1 5 V
DC output voltage accuracy IOUT= 0 mA –3.5% 3.5%
MOSFET
RON,H High side switch resistance 25°C, VPWR6_Boost – VPWR6_SWITCH = 5.5 V 150 mΩ
RON,L Low side switch resistance(2) 25°C 85 mΩ
LOAD CURRENT
Allowed Load Current PWR6(3). 2 A
IOCL Current limit(2)(3) LOUT= 3.3 μH 3.2 3.6 4.2 A
ON-TIME TIMER CONTROL
tON On time VIN = 12 V, VO = 5 V 120 ns
tOFF(MIN) Minimum off time(2) TA = 25°C, VFB = 0 V 270 310 ns
START-UP
Soft start 1 2.5 4 ms
PGOOD
RatioOV Overvoltage protection 120%
RatioPG Relative power good level Low to high 72%
AUXILIARY LDOs
VPWR3,4_VIN Input voltage range LDO1 (PWR4), LDO2 (PWR3) 3.3 12 20 V
PGOOD Power good PWR3,4_VOUT PWR3,4_VOUT rising 80%
PWR3,4_VOUT falling 60%
OVP Overvoltage Protection PWR3,4_VOUT 7 V
DC output voltage accuracy PWR3,4_VOUT IOUT= 0 mA –3% 3%
Regulator current limit(2) 300 340 400 mA
tON Turn-on time to 80% of VOUT = PWR3 and PWR4, C= 1 µF 40 µs
LDO2 (PWR3)
VPWR3_VOUT Output Voltage PWR3_VOUT 2.5 V
Load Current capability 200 mA
DC Load regulation PWR3_VOUT VOUT= 2.5 V, IOUT= 5 to 200 mA –70 mV/A
DC Line regulation PWR3_VOUT VOUT= 2.5 V, IOUT= 5 mA, PWR3_VIN = 3.3 to 20 V 30 µV/V
LDO1 (PWR4)
VPWR4_VOUT Output Voltage PWR4_VOUT 3.3 V
Load Current capability 200 mA
DC Load regulation PWR4_VOUT VOUT= 3.3 V, IOUT= 5 to 200 mA –70 mV/A
DC Line regulation PWR4_VOUT VOUT= 3.3V, IOUT= 5 mA, PWR4_VIN= 4 to 20 V 30 µV/V
Regulator dropout At 25 mA, VOUT= 3.3 V, VPWR4_VIN= 3.3 V 48 mV
MEASUREMENT SYSTEM
LABB
τRC Settling time To 1% of final value(2) 4.6 6.6 µs
To 0.1% of final value(2) 7 10
VACMPR_IN_LABB Input voltage range ACMPR_IN_LABB 0 1.5 V
Sampling window ACMPR_IN_LABB Programmable per 7 µs 7 28 µs
DIGITAL CONTROL - LOGIC LEVELS AND TIMING CHARACTERISTICS
VSPI_VIN SPI supply voltage range SPI_VIN 1.7 3.6 V
VOL Output low-level RESET_Z, ACMPR_OUT, CLK_OUT. IO = 0.3 mA sink current 0 0.3 V
SPI_DOUT. IO = 5 mA sink current 0 0.3 × VSPI_VIN
INT_Z. IO = 1.5 mA sink current 0 0.3 × VSPI_VIN
VOH Output high-level RESET_Z, ACMPR_OUT, CLK_OUT. IO = 0.3 mA source current 1.3 2.5 V
SPI_DOUT. IO = 5 mA source current 0.7 × VSPI_VIN VSPI_VIN
VIL Input low-level PROJ_ON, CH_SEL_0, CH_SEL_1 0 0.4 V
SPI_CSZ, SPI_CLK, SPI_DIN 0 0.3 × VSPI_VIN
VIH Input high-level PROJ_ON, CH_SEL_0, CH_SEL_1 1.2 V
SPI_CSZ, SPI_CLK, SPI_DIN 0.7 × VSPI_VIN VSPI_VIN
IBIAS Input bias current VIO= 3.3 V, any digital input pin 0.1 µA
SPI_CLK SPI clock frequency(4) Normal SPI mode, DIG_SPI_FAST_SEL = 0, ƒOSC = 9 MHz 0 36 MHz
Fast SPI mode, DIG_SPI_FAST_SEL = 1, VSPI_VIN> 2.3 V, ƒOSC = 9 MHz 20 40
tDEGLITCH Deglitch time CH_SEL_0, CH_SEL_1(2) 300 ns
INTERNAL OSCILLATOR
ƒOSC Oscillator frequency 9 MHz
Frequency accuracy TA= 0 °C to 70°C –5% 5%
THERMAL SHUTDOWN
TWARN Thermal warning (HOT threshold) 120 °C
Hysteresis 10
TSHTDWN Thermal shutdown (TSD threshold) 150 °C
Hysteresis 15
(1) Including rectifying diode
(2) Not production tested
(3) Care should be taken not to exceed the max power dissipation. Refer to Section 10.3.
(4) Maximum depends linearly on oscillator frequency fOSC.
(5) Take care that the capacitor has the specified capacitance at the related voltage, that is, VOFFSET, VBIAS, or VRESET.
(6) VIN must be higher than the UVLO voltage setting, including after accounting for AC noise on VIN, for the DLPA3005 to fully operate. While 6.0 V is the min VIN voltage supported, TI recommends that the UVLO is never set below 6.21 V for fault fast power down. 6.21 V gives margin above 6.0 V to protect against the case where someone suddenly removes VIN’s power supply which causes the VIN voltage to drop rapidly. Failure to keep VIN above 6.0V before the mirrors are parked and VOFS, VRST, and VBIAS supplies are properly shut down can result in permanent damage to the DMD. Since 6.21 V is .21 V above 6.0 V, when UVLO trips there is time for the DLPA3005 and DLPC343x to park the DMD mirrors and do a fast shut down of supplies VOFS, VRST, and VBIAS. For whatever UVLO setting is used, if VIN’s power supply is suddenly removed enough bulk capacitance should be included on VIN inside the projector to keep VIN above 6.0V for at least 100us after UVLO trips.
(7) UVLO should not be used for normal power down operation, it is meant as a protection from power loss.
(8) General purpose buck2 (PWR6) is currently supported.
(9) Supports up to 32 A for series LEDs based on reference hardware design.