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DLPA3082 は高集積パワー マネージメント IC であり、DLP®Pico™ プロジェクタ システム向けに最適化済みです。DLPA3082 には 5 つの降圧コンバータが内蔵され、そのうち 2 つは DLPC の低電圧電源専用です。もう 1 つの専用調整電源は、DMD 用の 3 つのタイミング クリティカルな DC 電源を生成します。VBIAS、VRST、VOFS です。
DLPA3082 は、柔軟に使える複数の補助ブロックを内蔵しています。これにより、カスタマイズされた Pico プロジェクタ システムを実現できます。1 つの 8 ビット プログラマブル降圧コンバータは、例えば補助電源ラインを作成するために使用されます。汎用 Buck2 (PWR6) が、現在サポートされています。2 つの LDO は、最大 200mA の低電流電源のために使用されます。これらの LDO は、2.5V および 3.3V に事前定義されています。
SPI を使って、DLPA3082 のすべてのブロックがアドレス指定されます。含まれる機能には、システム リセットの生成、電源シーケンス、IC の自己保護、外部 ADC にアナログ情報をルーティングするアナログ マルチプレクサがあります。
部品番号 | パッケージ | パッケージ サイズ |
---|---|---|
DLPA3082(1) | HTQFP (100) | 14.00mm × 14.00mm |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
N/C | 1 | — | No connect |
DRST_LS_IND | 2 | I/O | Connection for the DMD SMPS-inductor (low-side switch). |
DRST_5P5V | 3 | O | Filter pin for LDO DMD. Power supply for internal DMD reset regulator, typical 5.5V |
DRST_PGND | 4 | GND | Power ground for DMD SMPS. Connect to ground plane. |
DRST_VIN | 5 | POWER | Power supply input for LDO DMD. Connect to system power. |
DRST_HS_IND | 6 | I/O | Connection for the DMD SMPS-inductor (high-side switch). |
RESERVED | 7 | — | Connect a 10µF capacitor to ground. |
RESERVED | 8 | — | Connect a 1µF capacitor to ground. |
RESERVED | 9 | — | No connect |
RESERVED | 10 | — | No connect |
RESERVED | 11 | — | No connect |
RESERVED | 12 | — | No connect |
RESERVED | 13 | — | No connect |
RESERVED | 14 | — | No connect |
RESERVED | 15 | — | No connect |
RESERVED | 16 | — | No connect |
RESERVED | 17 | — | No connect |
RESERVED | 18 | — | No connect |
RESERVED | 19 | — | No connect |
RESERVED | 20 | — | No connect |
RESERVED | 21 | — | No connect |
RESERVED | 22 | — | No connect |
RESERVED | 23 | — | No connect |
RESERVED | 24 | — | No connect |
RESERVED | 25 | — | No connect |
RESERVED | 26 | — | No connect |
RESERVED | 27 | — | No connect |
RESERVED | 28 | — | No connect |
RESERVED | 29 | — | No connect |
RESERVED | 30 | — | No connect |
RESERVED | 31 | — | Connect a pull-down 1kΩ resistor to ground. |
GND | 32 | GND | Ground |
RESERVED | 33 | — | No connect |
RESERVED | 34 | — | No connect |
RESERVED | 35 | — | No connect |
RESERVED | 36 | — | Connect a pull-down 1kΩ resistor to ground. |
GND | 37 | GND | Ground |
RESERVED | 38 | — | No connect |
RESERVED | 39 | — | No connect |
RESERVED | 40 | — | No connect |
RESERVED | 41 | — | No connect |
THERMAL_PAD | 42 | GND | Thermal pad. Connect to a clean system ground. |
CLK_OUT | 43 | O | No connect. Reserved for color wheel clock output. |
CW_SPEED_PWM_OUT | 44 | O | No connect. Reserved for color wheel PWM output. |
SPI_VIN | 45 | I | Supply for SPI interface |
SPI_CLK | 46 | I | SPI clock input |
SPI_MISO | 47 | O | SPI data output |
SPI_SS_Z | 48 | I | SPI chip select (active low) |
SPI_MOSI | 49 | I | SPI data input |
PWR7_BOOST | 50 | I | No connect. Reserved for general purpose buck converter. Charge-pump-supply input for the high-side FET gate drive circuit. Connect a 100nF capacitor between PWR7_BOOST and PWR7_SWITCH pins. |
PWR7_FB | 51 | I | No connect. Reserved for general purpose buck converter. Converter feedback input. Connect to converter output voltage. |
PWR7_VIN | 52 | POWER | No connect. Reserved for general purpose buck converter. Power supply input for converter |
PWR7_SWITCH | 53 | I/O | No connect. Reserved for general purpose buck converter. Switch node connection between high-side NFET and low-side NFET |
PWR7_PGND | 54 | GND | No connect. Reserved for general purpose buck converter. Ground pin. Power ground return for switching circuit |
PROJ_ON | 55 | I | Input signal to enable and or disable the IC and DLP projector |
ACMPR_LABB_SAMPLE | 56 | I | Control signal to sample voltage at ACMPR_IN_LABB. Needs to connect a pull-down 10kΩ resistor to ground when the pin is not used. |
RESET_Z | 57 | O | Reset output to the DLP system (active low). The pin is held low to reset DLP system. |
INT_Z | 58 | O | Interrupt output signal (open drain, active low). Connect to the pullup resistor. |
DGND | 59 | GND | Digital ground. Connect to ground plane. |
CH_SEL_0 | 60 | I | Control signal to enable either of CH1,2,3. Needs to connect a pull-down 10kΩ resistor to ground when the pin is not used. |
CH_SEL_1 | 61 | I | Control signal to enable either of CH1,2,3. Needs to connect a pull-down 10kΩ resistor to ground when the pin is not used. |
PWR6_PGND | 62 | GND | Ground pin. Power ground return for switching circuit |
PWR6_SWITCH | 63 | I/O | Switch node connection between high-side NFET and low-side NFET |
PWR6_VIN | 64 | POWER | Power supply input for converter |
PWR6_BOOST | 65 | I | Charge-pump-supply input for the high-side FET gate drive circuit. Connect a 100nF capacitor between PWR6_BOOST and PWR6_SWITCH pins. |
PWR6_FB | 66 | I | Converter feedback input. Connect to output voltage. |
PWR5_VIN | 67 | POWER | No connect. Reserved for general purpose buck converter. Power supply input for converter |
PWR5_SWITCH | 68 | I/O | No connect. Reserved for general purpose buck converter. Switch node connection between high-side NFET and low-side NFET |
PWR5_BOOST | 69 | I | No connect. Reserved for general purpose buck converter. Charge-pump-supply input for the high-side FET gate drive circuit. Connect 100nF capacitor between PWR5_BOOST and PWR5_SWITCH pins. |
PWR5_PGND | 70 | GND | No connect. Reserved for general purpose buck converter. Ground pin. Power ground return for switching circuit |
PWR5_FB | 71 | I | No connect. Reserved for general purpose buck converter. Converter feedback input. Connect to output voltage. |
PWR2_FB | 72 | I | Converter feedback input. Connect to output voltage. |
PWR2_PGND | 73 | GND | Ground pin. Power ground return for switching circuit |
PWR2_SWITCH | 74 | I/O | Switch node connection between high-side NFET and low-side NFET |
PWR2_VIN | 75 | POWER | Power supply input for converter |
PWR2_BOOST | 76 | I | Charge-pump-supply input for the high-side FET gate drive circuit. Connect a 100nF capacitor between PWR2_BOOST and PWR2_SWITCH pins. |
ACMPR_IN_1 | 77 | I | Reserved. Input for analog sensor signal. No connect when the pin is not used. |
ACMPR_IN_2 | 78 | I | Input for analog sensor signal. No connect when the pin is not used. |
ACMPR_IN_3 | 79 | I | Input for analog sensor signal. No connect when the pin is not used. |
ACMPR_IN_LABB | 80 | I | Input for ambient light sensor, sampled input. No connect when the pin is not used. |
ACMPR_OUT | 81 | O | Analog comparator out. No connect when the pin is not used. |
ACMPR_REF | 82 | I | Reference voltage input for analog comparator. No connect when the pin is not used. |
PWR_VIN | 83 | POWER | Power supply input for LDO_Bucks. Connect to system power. |
PWR_5P5V | 84 | O | Filter pin for LDO_BUCKS. Internal analog supply for buck converters, typical 5.5V |
VINA | 85 | POWER | Input voltage supply pin for reference system |
AGND | 86 | GND | Analog ground pin |
PWR3_OUT | 87 | O | Filter pin for LDO_2 DMD/DLPC/AUX, typical 2.5V |
PWR3_VIN | 88 | POWER | Power supply input for LDO_2. Connect to system power. |
PWR4_OUT | 89 | O | Filter pin for LDO_1 DMD/DLPC/AUX, typical 3.3V |
PWR4_VIN | 90 | POWER | Power supply input for LDO_1. Connect to system power. |
SUP_2P5V | 91 | O | Filter pin for LDO_V2V5. Internal supply voltage, typical 2.5V |
SUP_5P0V | 92 | O | Filter pin for LDO_V5V. Internal supply voltage, typical 5V |
PWR1_PGND | 93 | GND | Ground pin. Power ground return for switching circuit |
PWR1_FB | 94 | I | Converter feedback input. Connect to output voltage. |
PWR1_SWITCH | 95 | I/O | Switch node connection between high-side NFET and low-side NFET |
PWR1_VIN | 96 | POWER | Power supply input for converter |
PWR1_BOOST | 97 | I | Charge-pump-supply input for the high-side FET gate drive circuit. Connect a 100nF capacitor between PWR1_BOOST and PWR1_SWITCH pins. |
DMD_VOFFSET | 98 | O | VOFS output rail. Connect to ceramic capacitor. |
DMD_VBIAS | 99 | O | VBIAS output rail. Connect to ceramic capacitor. |
DMD_VRESET | 100 | O | VRESET output rail. Connect to ceramic capacitor. |