JAJSF34B November 2017 – May 2022 DLPC120-Q1
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
All signals should follow a 0.005-in width 0.015-in spacing design rule. Minimum trace clearance from the ground ring around the PCB shall be 0.1-in minimum. Actual trace widths and clearances will be determined based on an analysis of impedance and stack-up requirements, some variation is expected.
GROUP | SIGNAL | CONSTRAINTS(1) |
---|---|---|
DDR2 I/F | MEM_CLK MEM_CLKZ MEM_DQS0 MEM_DQSZ0 MEM_DQS1 MEM_DQSZ1 | Lengths Matched to 25 mils Max Total Length: 1500 mils Impedance: 100-Ω differential (± 10%) |
MEM_DQ[0:15] | Lengths Matched to 50 mils Max Total Length: 1500 mils Impedance: 50 Ω (± 10%) | |
MEM_RASZ MEM_CASZ MEM_WEZ MEM_CSZ MEM_CKE MEM_A[0:12] | Lengths Matched to 100 mils Max Total Length: 1500 mils Impedance: 50 Ω (± 10%) | |
DMD I/F | DMD_D[0:14] DMD_DCLK DMD_BUS DMD_STRB DMD_OEZ DMD_LOADB DMD_SAC_CLK DMD_SAC_BUS DMD_SCTRL DMD_TRC DMD_JTCK DMD_JTDI DMD_JTDO DMD_JTMS | Lengths Matched to 50 mils Max Total Length: 10000 mils Impedance: 50 Ω (± 10%) |
Serial Flash I/F | FLASH_DCLK, FLASH_POCI, FLASH_PICO, FLASH_CSZ | Lengths Matched to 100 mils Max Total Length: 2500 mils Impedance: 50 Ω (± 10%) |