JAJSF34B November   2017  – May 2022 DLPC120-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 LED Driver Interface
    2. 5.2 DMD Temperature Interface
    3.     General Purpose I/O
    4. 5.3 Main Video and Data Control Interface
    5. 5.4 DMD Interface
    6. 5.5 Memory Interface
    7.     Board Level Test and Debug
    8.     Manufacturing Test Support
    9.     Test Point Interface
    10.     Power and Ground
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics for I/O
    7. 6.7  Power Supply and Reset Timing Requirements
    8. 6.8  Reference Clock PLL Timing Requirements
    9. 6.9  Parallel Interface General Timing Requirements
    10. 6.10 Parallel Interface Frame Timing Requirements
    11. 6.11 Flash Memory Interface Timing Requirements
    12. 6.12 DMD Interface Timing Requirements
    13. 6.13 JTAG Interface Timing Requirements
    14. 6.14 I2C Interface Timing Requirements
  7. 7 Parameter Measurement Information
    1. 7.1 Parallel Interface Input Source Timing
    2. 7.2 Design for Test Functions
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Serial Flash Interface
      2. 8.3.2 Serial Flash Programming
      3. 8.3.3 DDR2 Memory Interface
      4. 8.3.4 JTAG and DMD Interface Test
      5. 8.3.5 Temperature Monitor Function
      6. 8.3.6 Host Command Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Video Mode
      2. 8.4.2 Splash Screen Mode
      3. 8.4.3 Test Pattern Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB layout guidelines for internal ASIC PLL power
      2. 11.1.2 DLPC120-Q1 Reference Clock
        1. 11.1.2.1 Recommended Crystal Oscillator Configuration
      3. 11.1.3 General PCB Recommendations
      4. 11.1.4 PCB Routing Guidelines
      5. 11.1.5 Number of Layer Changes
      6. 11.1.6 Terminations
      7. 11.1.7 General Handling Guidelines for Unused CMOS-Type Pins
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Device Support
      1. 12.2.1 Device Nomenclature
        1. 12.2.1.1 Device Markings
    3. 12.3 Documentation Support
      1. 12.3.1 Related Documentation
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 サポート・リソース
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ZXS|216
サーマルパッド・メカニカル・データ
発注情報

9.2.1 Design Requirements

The Figure 9-1 shows a typical projector application. For this application, the DLPC120-Q1 is controlled by a separate control processor, and the image data is received through the parallel RGB interface.

As with prior DLP® electronics solutions, image data is 100% digital from the DLPC120-Q1 input port to the image projected on to the display screen. The image stays in digital form and is never converted into an analog signal. The DLPC120-Q1 processes the digital input image and converts the data into a bit-plane format, as needed by the DMD. The DMD then reflects light to the screen using binary pulse-width-modulation (PWM) for each pixel mirror. The viewer’s eyes integrate this light to form brilliant, crisp images.

The DLPC120-Q1 provides signals that enable red, green, and blue LEDs to synchronize to the DMD PWM bit planes. These signals combined with an external MCU (TMS320F28023) can be used to create a very high dynamic dimming range necessary for automotive heads-up display (HUD) applications.

The DLPC120-Q1 also features temperature monitoring of the DMD in order to automatically park the micromirrors when the DMD temperature is beyond the operating range.

The DLPC120-Q1 uses the DDR2 SDRAM as a frame buffer to convert RGB video data into the necessary bit plane format required by the DMD. The DLPC120-Q1 also supports multiple input resolutions and scales them to match the native .3" WVGA DMD format. These images can also be electronically bezel-adjusted on the DMD, which could allow the displayed image to be electronically adjusted for mechanical misalignment. The DLPC120-Q1 is configured at power up with data stored in the Flash memory via SPI. The Flash interface is the primary method to configure the controller.

The DLPC120-Q1 supports system diagnostic and self-check features, such as video detection, DDR2 memory Built-in Self Test (BIST), System BIST, Flash BIST, and JTAG (in system and DMD interface).

Due to the mechanical nature of the micromirrors, the latency of the DMD and DLPC120-Q1 chipset is fixed across all temperature and operating conditions. The observed video latency is one frame, or 16.67 ms at an input frame rate of 60 Hz. However, please note that the use of the DLPC120-Q1 bezel adjustment feature, if enabled, requires an additional frame of processing.

Contact a TI Applications Engineer in order to gain access to a fully functional reference design based on the DLP30xx-Q1 chipset.