JAJSF34B November 2017 – May 2022 DLPC120-Q1
PRODUCTION DATA
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The DLPC120-Q1 has two test interfaces using JTAG protocol:
Using the DMD JTAG function, the DMD interface signals are toggled, and the connection at the DMD is verified by using the DMD JTAG signals to sample the inputs, and then toggled back to the DLPC120-Q1 for comparison to expected values. All DMD logic signals, except DAD OEZ, are tested individually for stuck high or low independently. Alternating data pattern for adjacent pins, as well as "walking 1’s" and "walking 0’s" patterns are used during the test. The DAD_OEZ is only tested in the high state as asserting this signal and toggling the inputs could cause damage to the DMD. Refer to Figure 8-3 for recommended connections for the DLPC120-Q1 boundary scan test configuration. Refer to Figure 8-4 for recommended connections of the DLPC120-Q1 to DMD interface test. For additional information about the DMD Boundary scan function refer to the specific DMD device datasheet.