JAJSF34B November   2017  – May 2022 DLPC120-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 LED Driver Interface
    2. 5.2 DMD Temperature Interface
    3.     General Purpose I/O
    4. 5.3 Main Video and Data Control Interface
    5. 5.4 DMD Interface
    6. 5.5 Memory Interface
    7.     Board Level Test and Debug
    8.     Manufacturing Test Support
    9.     Test Point Interface
    10.     Power and Ground
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics for I/O
    7. 6.7  Power Supply and Reset Timing Requirements
    8. 6.8  Reference Clock PLL Timing Requirements
    9. 6.9  Parallel Interface General Timing Requirements
    10. 6.10 Parallel Interface Frame Timing Requirements
    11. 6.11 Flash Memory Interface Timing Requirements
    12. 6.12 DMD Interface Timing Requirements
    13. 6.13 JTAG Interface Timing Requirements
    14. 6.14 I2C Interface Timing Requirements
  7. 7 Parameter Measurement Information
    1. 7.1 Parallel Interface Input Source Timing
    2. 7.2 Design for Test Functions
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Serial Flash Interface
      2. 8.3.2 Serial Flash Programming
      3. 8.3.3 DDR2 Memory Interface
      4. 8.3.4 JTAG and DMD Interface Test
      5. 8.3.5 Temperature Monitor Function
      6. 8.3.6 Host Command Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Video Mode
      2. 8.4.2 Splash Screen Mode
      3. 8.4.3 Test Pattern Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB layout guidelines for internal ASIC PLL power
      2. 11.1.2 DLPC120-Q1 Reference Clock
        1. 11.1.2.1 Recommended Crystal Oscillator Configuration
      3. 11.1.3 General PCB Recommendations
      4. 11.1.4 PCB Routing Guidelines
      5. 11.1.5 Number of Layer Changes
      6. 11.1.6 Terminations
      7. 11.1.7 General Handling Guidelines for Unused CMOS-Type Pins
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Device Support
      1. 12.2.1 Device Nomenclature
        1. 12.2.1.1 Device Markings
    3. 12.3 Documentation Support
      1. 12.3.1 Related Documentation
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 サポート・リソース
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
  • ZXS|216
サーマルパッド・メカニカル・データ
発注情報

6.12 DMD Interface Timing Requirements

MINNOMMAXUNIT
ƒclockClock frequency, DMD_DCLK and DMD_SAC_CLK(1)75.0078.0080.00MHz
tp_clkperClock period, DMD_DCLK and DMD_SAC_CLK50% reference points12.515.0ns
tp_clkjitClock jitter, DMD_DCLK and DMD_SAC_CLKMaximum fclock200ps
tp_whPulse width high, DMD_DCLK and DMD_SAC_CLK50% reference points6.2ns
tp_wlPulse width low, DMD_DCLK and DMD_SAC_CLK50% reference points6.2ns
ttTransition time, all signals20% to 80% reference points0.51.5ns
tp_suOutput setup time – DMD_D(14:0), DMD_SCTRL, DMD_LOADB and DMD_TRC relative to both rising and falling edges of DMD_DCLK(2)50% reference points1.5ns
tp_hOutput hold time – DMD_D(14:0), DMD_SCTRL, DMD_LOADB and DMD_TRC signals relative to both rising and falling edges of DMD_DCLK(2)50% reference points1.5ns
tp_d1_skewDMD data skew – DMD_D(14:0), DMD_SCTRL, DMD_LOADB and DMD_TRC signals relative to each other50% reference points0.20ns
tp_d2_skewDAD/ SAC data skew - DMD_SAC_BUS, DMD_DAD_OEZ and DMD_DAD_BUS signals relative to DMD_SAC_CLK50% reference points1.65ns
tp_d3_skewDMD_DAD_STRB  signal relative to DMD_DCLK50% reference points1.65ns
tp_clk_skewClock skew –  DMD_DCLK and DMD_SAC_CLK relative to each other50% reference points0.25ns
(1) This range includes the 200 PPM of the external oscillator.
(2) Output setup and hold numbers already account for ASIC clock jitter. Only routing skew and DMD setup/ hold need be considered in system timing analysis.
GUID-AA5733B2-D98B-4B99-AC7F-C171FE591CC2-low.gifFigure 6-6 DMD Interface Timing