JAJSJA1E August   2020  – August 2024 DLPC230S-Q1 , DLPC231S-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Electrical Characteristics for Fixed Voltage I/O
    7. 5.7  DMD High-Speed SubLVDS Electrical Characteristics
    8. 5.8  DMD Low-Speed SubLVDS Electrical Characteristics
    9. 5.9  OpenLDI LVDS Electrical Characteristics
    10. 5.10 Power Dissipation Characterisics
    11. 5.11 System Oscillators Timing Requirements
    12. 5.12 Power Supply and Reset Timing Requirements
    13. 5.13 Parallel Interface General Timing Requirements
    14. 5.14 OpenLDI Interface General Timing Requirements
    15. 5.15 Parallel/OpenLDI Interface Frame Timing Requirements
    16. 5.16 Host/Diagnostic Port SPI Interface Timing Requirements
    17. 5.17 Host/Diagnostic Port I2C Interface Timing Requirements
    18. 5.18 Flash Interface Timing Requirements
    19. 5.19 TPS99000S-Q1 SPI Interface Timing Requirements
    20. 5.20 TPS99000S-Q1 AD3 Interface Timing Requirements
    21. 5.21 DLPC23xS-Q1 I2C Port Interface Timing Requirements
    22. 5.22 Chipset Component Usage Specification
  7. 6 Parameter Measurement Information
    1. 6.1 HOST_IRQ Usage Model
    2. 6.2 Input Source
      1. 6.2.1 Supported Input Sources
      2. 6.2.2 Parallel Interface Supported Data Transfer Formats
        1. 6.2.2.1 OpenLDI Interface Supported Data Transfer Formats
          1. 6.2.2.1.1 OpenLDI Interface Bit Mapping Modes
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Parallel Interface
      2. 7.3.2  OpenLDI Interface
      3. 7.3.3  DMD (SubLVDS) Interface
      4. 7.3.4  Serial Flash Interface
      5. 7.3.5  Serial Flash Programming
      6. 7.3.6  Host Command and Diagnostic Processor Interfaces
      7. 7.3.7  GPIO Supported Functionality
      8. 7.3.8  Built-In Self Test (BIST)
      9. 7.3.9  EEPROMs
      10. 7.3.10 Temperature Sensor
      11. 7.3.11 Debug Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Display Mode
      3. 7.4.3 Calibration Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Head-Up Display
        1. 8.2.1.1 Design Requirements
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Management
      2. 8.3.2 Hot Plug Usage
      3. 8.3.3 Power Supply Filtering
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1  PCB Layout Guidelines for Internal ASIC PLL Power
        2. 8.4.1.2  DLPC23xS-Q1 Reference Clock
          1. 8.4.1.2.1 Recommended Crystal Oscillator Configuration
        3. 8.4.1.3  DMD Interface Layout Considerations
        4. 8.4.1.4  General PCB Recommendations
        5. 8.4.1.5  General Handling Guidelines for Unused CMOS-Type Pins
        6. 8.4.1.6  Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
        7. 8.4.1.7  Number of Layer Changes
        8. 8.4.1.8  Stubs
        9. 8.4.1.9  Terminations
        10. 8.4.1.10 Routing Vias
      2. 8.4.2 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Device Nomenclature
        1. 9.1.2.1 Device Markings DLPC230-Q1 or DLPC230S-Q1
        2. 9.1.2.2 Device Markings DLPC231-Q1 or DLPC231S-Q1
        3. 9.1.2.3 Video Timing Parameter Definitions
    2. 9.2 Trademarks
    3. 9.3 静電気放電に関する注意事項
    4. 9.4 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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発注情報

5.12 Power Supply and Reset Timing Requirements

MIN MAX UNIT
TPS99000S-Q1 REQUIREMENTS(1)
tramp Power supply ramp time(2) Power supply ramp to minimum recommended operating voltage 0.5 10 ms
tps_aln 1.1V Power Supply Alignment(3) Leading edge for application or removal of power. Each 1.1V power supply to the DLPC23xS-Q1 must be applied simultaneously within this time. 10 µs
trst RESETZ low to Power Supply disable(4) Leading edge for removal of power 1.0 µs
tw(L1) Pulse duration, active low, RESETZ(4) 95% power to 50% RESETZ reference point
At initial application of power		 5.0 ms
tw(L2) Pulse duration, active low, RESETZ 50% to 50% reference points (RESETZ)
Subsequent resets after initial application of power		 1.0 µs
tt Transition time, RESETZ, tt = tƒ and tr 20% to 80% reference points (signal) 6 µs
(1) The TPS99000S-Q1 controls power supply timing for the DLPC23xS-Q1. Refer to the TPS99000S-Q1 System Management and Illumination Controller Data Sheet for additional system power timing requirements.
(2) Power supplies do not need to ramp simultaneously, but each supply must reach its minimum voltage within the maximum ramp time specified.
(3) The DLPC23xS-Q1 does not require specific sequencing or alignment of 1.8V and 3.3V supplies. However, the TPS99000S-Q1 enforces sequencing of the 1.1V, 1.8V, and 3.3V voltage rails. The following describes DLPC23xS-Q1 behavior when the voltage rails are not brought up simultaneously:
  • VCCK (1.1V core) Power = On, I/O Power = Off, RESETZ = '0': While this condition exists, additional leakage current can be drawn, and all outputs are unknown (likely to be a weak "low").
  • VCCK (1.1V core) Power = Off, I/O Power = On, RESETZ = '0': While this condition exists all outputs are tristated.
Neither of these two conditions will impact normal DLPC23xS-Q1 reliability.
(4) RESETZ must be held low if any supply (Core or I/O) is less than its minimum specified on value. For more information on RESETZ, see Section 4.
DLPC230S-Q1 DLPC231S-Q1 Power Supply and RESETZ Timing Figure 5-2 Power Supply and RESETZ Timing