JAJSMW5A October   2021  – January 2022 DLPC3421

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 6.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 6.9  DMD Low-Speed Interface Electrical Characteristics
    10. 6.10 System Oscillator Timing Requirements
    11. 6.11 Power Supply and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 BT656 Interface General Timing Requirements
    15. 6.15 DSI Host Timing Requirements
    16. 6.16 Flash Interface Timing Requirements
    17. 6.17 Other Timing Requirements
    18. 6.18 DMD Sub-LVDS Interface Switching Characteristics
    19. 6.19 DMD Parking Switching Characteristics
    20. 6.20 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Source Requirements
        1. 7.3.1.1 Supported Resolution and Frame Rates
        2. 7.3.1.2 Parallel Interface
          1. 7.3.1.2.1 PDATA Bus – Parallel Interface Bit Mapping Modes
        3. 7.3.1.3 DSI Interface
      2. 7.3.2 Device Startup
      3. 7.3.3 SPI Flash
        1. 7.3.3.1 SPI Flash Interface
        2. 7.3.3.2 SPI Flash Programming
      4. 7.3.4 I2C Interface
      5. 7.3.5 Content Adaptive Illumination Control (CAIC)
      6. 7.3.6 Test Point Support
      7. 7.3.7 DMD Interface
        1. 7.3.7.1 Sub-LVDS (HS) Interface
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 PLL Design Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 Power-Up Initialization Sequence
    4. 9.4 DMD Fast Park Control (PARKZ)
    5. 9.5 Hot Plug I/O Usage
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  PLL Power Layout
      2. 10.1.2  Reference Clock Layout
        1. 10.1.2.1 Recommended Crystal Oscillator Configuration
      3. 10.1.3  DSI Interface Layout
      4. 10.1.4  Unused Pins
      5. 10.1.5  DMD Control and Sub-LVDS Signals
      6. 10.1.6  Layer Changes
      7. 10.1.7  Stubs
      8. 10.1.8  Terminations
      9. 10.1.9  Routing Vias
      10. 10.1.10 Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
      3. 11.1.3 Video Timing Parameter Definitions
    2. 11.2 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. 13Package Option Addendum
    1. 13.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
over operating free-air temperature range (unless otherwise noted)
MINNOMMAXUNIT
V(VDD)Core power 1.1 V (main 1.1 V)1.0451.101.155V
V(VDDLP12)DSI PHY low power mode driver supplySee (3)(4)1.0451.101.155V
V(VCC18)All 1.8-V I/O power:
(1.8-V power supply for RESETZ, PARKZ LED_SEL, CMP_OUT, GPIO, IIC1, TSTPT, and JTAG pins.)		1.641.801.96V
V(VCC_INTF)Host or parallel interface I/O power: 1.8 to 3.3 V (includes IIC0, PDATA, video syncs, and HOST_IRQ pins)See (1)1.641.801.96V
2.282.502.72
3.023.303.58
V(VCC_FLSH)Flash interface I/O power: 1.8 to 3.3 VSee (1)1.641.801.96V
2.282.502.72
3.023.303.58
V(VDD_PLLM)MCG PLL 1.1-V powerSee (2)1.0251.1001.155V
V(VDD_PLLD)DCG PLL 1.1-V powerSee (2)1.0251.1001.155V
TAOperating ambient temperature(5)–3085°C
TJOperating junction temperature–30105°C
(1) These supplies have multiple valid ranges.
(2) The minimum voltage is lower than other 1.1-V supply minimum to enable additional filtering. This filtering may result in an IR drop across the filter.
(3) It is recommended that VDDLP12 rail is tied to the VDD rail. The DSI LP supply (VDDLP12) is only used for read responses from the controller which are not supported. Because of this, a separate 1.2-V rail is not required. If a separate 1.2-V supply is already being used to power this rail, a voltage tolerance of ±6.67% is allowed on this separate 1.2-V supply.
(4) When the DSI-PHY LP supply (VDDLP12) is fed from a supply separate from VDD, the VDDLP12 power must sequence ON after the 1.1-V core supply and must sequence OFF before the 1.1-V core supply.
(5) The operating ambient temperature range assumes 0 forced air flow, a JEDEC JESD51 junction-to-ambient thermal resistance value at 0 forced air flow (RθJA at 0 m/s), a JEDEC JESD51 standard test card and environment, along with minimum and maximum estimated power dissipation across process, voltage, and temperature. Thermal conditions vary by application, and this affects RθJA. Thus, maximum operating ambient temperature varies by application.
  • Ta_min = Tj_min – (Pd_min × RθJA) = –30°C – (0.0 W × 30.3°C/W) = –30°C
  • Ta_max = Tj_max – (Pd_max × RθJA) = +105°C – (0.348 W × 30.3°C/W) = +94.4°C