JAJSFP6B
July 2018 – October 2020
DLPC3434
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
5.1
Test Pins and General Control
5.2
Parallel Port Input
5.3
DSI Input Data and Clock
5.4
DMD Reset and Bias Control
5.5
DMD Sub-LVDS Interface
5.6
Peripheral Interface
5.7
GPIO Peripheral Interface
5.8
Clock and PLL Support
5.9
Power and Ground
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Power Electrical Characteristics
6.6
Pin Electrical Characteristics
6.7
Internal Pullup and Pulldown Electrical Characteristics
6.8
DMD Sub-LVDS Interface Electrical Characteristics
6.9
DMD Low-Speed Interface Electrical Characteristics
6.10
System Oscillator Timing Requirements
6.11
Power Supply and Reset Timing Requirements
6.12
Parallel Interface Frame Timing Requirements
6.13
Parallel Interface General Timing Requirements
6.14
Flash Interface Timing Requirements
6.15
Other Timing Requirements
6.16
DMD Sub-LVDS Interface Switching Characteristics
6.17
DMD Parking Switching Characteristics
6.18
Chipset Component Usage Specification
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Input Source Requirements
7.3.1.1
Supported Resolution and Frame Rates
7.3.1.2
Parallel Interface Data Transfer Format
7.3.1.3
3D Display
7.3.2
Device Startup
7.3.3
SPI Flash
7.3.3.1
SPI Flash Interface
7.3.3.2
SPI Flash Programming
7.3.4
I2C Interface
7.3.5
Content Adaptive Illumination Control (CAIC)
7.3.6
Local Area Brightness Boost (LABB)
7.3.7
3D Glasses Operation
7.3.8
Test Point Support
7.3.9
DMD Interface
7.3.9.1
Sub-LVDS (HS) Interface
7.4
Device Functional Modes
7.5
Programming
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curve
9
Power Supply Recommendations
9.1
PLL Design Considerations
9.2
System Power-Up and Power-Down Sequence
9.3
Power-Up Initialization Sequence
9.4
DMD Fast Park Control (PARKZ)
9.5
Hot Plug I/O Usage
10
Layout
10.1
Layout Guidelines
10.1.1
PLL Power Layout
10.1.2
Reference Clock Layout
10.1.2.1
Recommended Crystal Oscillator Configuration
10.1.3
Unused Pins
10.1.4
DMD Control and Sub-LVDS Signals
10.1.5
Layer Changes
10.1.6
Stubs
10.1.7
Terminations
10.1.8
Routing Vias
10.1.9
Thermal Considerations
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.1.1
Third-Party Products Disclaimer
11.1.2
Device Nomenclature
11.1.2.1
Device Markings
11.1.2.2
Video Timing Parameter Definitions
11.2
Documentation Support
11.2.1
Related Documentation
11.3
Related Links
11.4
Receiving Notification of Documentation Updates
11.5
Support Resources
11.6
Trademarks
12
Mechanical, Packaging, and Orderable Information
12.1
Package Option Addendum
12.1.1
Packaging Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
ZVB|176
MPBGA38B
サーマルパッド・メカニカル・データ
発注情報
jajsfp6b_oa
11.5
Support Resources