JAJSHL3E February   2014  – November 2020 DLPC3433 , DLPC3438

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Test Pins and General Control
    2. 5.2 Parallel Port Input
    3. 5.3 DSI Input Data and Clock
    4. 5.4 DMD Reset and Bias Control
    5. 5.5 DMD Sub-LVDS Interface
    6. 5.6 Peripheral Interface
    7. 5.7 GPIO Peripheral Interface
    8. 5.8 Clock and PLL Support
    9. 5.9 Power and Ground
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 6.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 6.9  DMD Low-Speed Interface Electrical Characteristics
    10. 6.10 System Oscillator Timing Requirements
    11. 6.11 Power Supply and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 BT656 Interface General Timing Requirements
    15. 6.15 DSI Host Timing Requirements
    16. 6.16 Flash Interface Timing Requirements
    17. 6.17 Other Timing Requirements
    18. 6.18 DMD Sub-LVDS Interface Switching Characteristics
    19. 6.19 DMD Parking Switching Characteristics
    20. 6.20 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Source Requirements
        1. 7.3.1.1 Supported Resolution and Frame Rates
        2. 7.3.1.2 3D Display
        3. 7.3.1.3 Parallel Interface
          1. 7.3.1.3.1 PDATA Bus – Parallel Interface Bit Mapping Modes
        4. 7.3.1.4 DSI Interface
      2. 7.3.2 Device Startup
      3. 7.3.3 SPI Flash
        1. 7.3.3.1 SPI Flash Interface
        2. 7.3.3.2 SPI Flash Programming
      4. 7.3.4 I2C Interface
      5. 7.3.5 Content Adaptive Illumination Control (CAIC)
      6. 7.3.6 Local Area Brightness Boost (LABB)
      7. 7.3.7 3D Glasses Operation
      8. 7.3.8 Test Point Support
      9. 7.3.9 DMD Interface
        1. 7.3.9.1 Sub-LVDS (HS) Interface
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 PLL Design Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 Power-Up Initialization Sequence
    4. 9.4 DMD Fast Park Control (PARKZ)
    5. 9.5 Hot Plug I/O Usage
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  PLL Power Layout
      2. 10.1.2  Reference Clock Layout
        1. 10.1.2.1 Recommended Crystal Oscillator Configuration
      3. 10.1.3  DSI Interface Layout
      4. 10.1.4  Unused Pins
      5. 10.1.5  DMD Control and Sub-LVDS Signals
      6. 10.1.6  Layer Changes
      7. 10.1.7  Stubs
      8. 10.1.8  Terminations
      9. 10.1.9  Routing Vias
      10. 10.1.10 Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
        2. 11.1.2.2 Video Timing Parameter Definitions
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
      2. 11.2.2 Related Links
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

5.7 GPIO Peripheral Interface

PIN(1) I/O TYPE(3) DESCRIPTION(2)
NAME NO.
GPIO_19 M15 I/O 1 General purpose I/O 19 (hysteresis buffer). Optional GPIO. If unused, TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_18 M14 I/O 1 General purpose I/O 18 (hysteresis buffer). Options:
  1. Optional GPIO. If unused, TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
  2. MTR_SENSE, Motor Sense (Input): For focus motor control applications, this GPIO must be configured as an input to the DLPC34xx and supplied from the focus motor position sensor.
GPIO_17 L15 I/O 1 General purpose I/O 17 (hysteresis buffer). Optional GPIO. If unused, TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_16 L14 I/O 1 General purpose I/O 16 (hysteresis buffer). Optional GPIO. If unused, TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_15 K15 I/O 1 General purpose I/O 15 (hysteresis buffer). Optional GPIO. If unused, TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_14 K14 I/O 1 General purpose I/O 14 (hysteresis buffer). Optional GPIO. If unused, TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_13 J15 I/O 1 General purpose I/O 13 (hysteresis buffer). Optional GPIO. If unused, TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_12 J14 I/O 1 General purpose I/O 12 (hysteresis buffer). Optional GPIO. If unused, TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_11 H15 I/O 1 General purpose I/O 11 (hysteresis buffer). Options:
  1. Thermistor power enable (output). Turns on the power to the thermistor when it is used and enabled.
  2. Optional GPIO. If unused, TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_10 H14 I/O 1 General purpose I/O 10 (hysteresis buffer). Options:
  1. RC_CHARGE (output): Intended to feed the RC charge circuit of the thermistor interface.
  2. Optional GPIO. If unused, TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_09 G15 I/O 1 General purpose I/O 09 (hysteresis buffer). Optional GPIO. If unused, TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_08 G14 I/O 1 General purpose I/O 08 (hysteresis buffer). Normal mirror parking request (active low): To be driven by the PROJ_ON output of the host. A logic low on this signal causes the DLPC34xx to PARK the DMD, but it does not power down the DMD (the DLPAxxxx does that instead). The minimum high time is 200 ms. The minimum low time is 200 ms.
GPIO_07 F15 I/O 1 General purpose I/O 07 (hysteresis buffer). If unused, TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_06 F14 I/O 1 General purpose I/O 06 (hysteresis buffer). Optional GPIO. If unused, TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_05 E15 I/O 1 General purpose I/O 05 (hysteresis buffer). Optional GPIO. If unused, TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_04 E14 I/O 1 General purpose I/O 04 (hysteresis buffer). Options:
  1. 3D glasses control (output): Controls the shutters on 3D glasses (Left = 1, Right = 0).
  2. SPI1_CSZ1 (active-low output): Optional SPI1 chip select 1 signal. Requires an external pullup resistor to deactivate this signal during reset and auto-initialization processes.
  3. Optional GPIO. If unused, TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_03 D15 I/O 1 General purpose I/O 03 (hysteresis buffer). SPI1_CSZ0 (active low output): SPI1 chip select 0 signal. This pin is typically connected to the DLPAxxxx SPI_CSZ pin. Requires an external pullup resistor to deactivate this signal during reset and auto-initialization processes.
GPIO_02 D14 I/O 1 General purpose I/O 02 (hysteresis buffer). Options:
  1. SPI1_DOUT (output): SPI1 data output signal. This pin is typically connected to the DLPAxxxx SPI_DIN pin.
  2. Optional DSI bus width config 1 (input): The controller samples this pin during boot and is used to define the number of lanes used for DSI operation. Requires an external pullup or pulldown resistor to configure as defined in Table 5-1. After boot, this GPIO pin will continue to be used as SPI1_DOUT. Select the external pullup or pulldown resistor to not interfere.
GPIO_01 C15 I/O 1 General purpose I/O 01 (hysteresis buffer). Options:
  1. SPI1_CLK (output): SPI1 clock signal. This pin is typically connected to the DLPAxxxx SPI_CLK pin.
  2. Optional DSI bus width config 0 (input): The controller samples this pin during boot and is used to define the number of lanes used for DSI operation. Requires an external pullup or pulldown resistor to configure as defined in Table 5-1. After boot, this GPIO pin will continue to be used as SPI1_CLK. Select the external pullup or pulldown resistor to not interfere.
GPIO_00 C14 I/O 1 General purpose I/O 00 (hysteresis buffer). SPI1_DIN (input): SPI1 data input signal. This pin is typically connected to the DLPAxxxx SPI_DOUT pin.
(1) GPIO pins must be configured through software for input, output, bidirectional, or open-drain operation. Some GPIO pins have one or more alternative use modes, which are also software configurable. An external pullup resistor is required for each signal configured as open-drain.
(2) General purpose I/O for the DLPC3433 and DLPC3438 controllers. These GPIO pins are software configurable.
(3) See Table 5-2 for type definitions.
Table 5-1 GPIO_01 and GPIO_02
GPIO_02 GPIO_01 Number of DSI Data Lanes
DSI-Lane-Config_1 DSI-Lane-Config_0
0 0 1
0 1 2
1 0 3
1 1 4