JAJSHK3E November   2014  – February 2021 DLPC3439

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 6.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 6.9  DMD Low-Speed Interface Electrical Characteristics
    10. 6.10 System Oscillator Timing Requirements
    11. 6.11 Power Supply and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 Flash Interface Timing Requirements
    15. 6.15 Other Timing Requirements
    16. 6.16 DMD Sub-LVDS Interface Switching Characteristics
    17. 6.17 DMD Parking Switching Characteristics
    18. 6.18 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Source Requirements
        1. 7.3.1.1 Supported Resolution and Frame Rates
        2. 7.3.1.2 3D Display
        3. 7.3.1.3 Parallel Interface
          1. 7.3.1.3.1 PDATA Bus – Parallel Interface Bit Mapping Modes
      2. 7.3.2 Device Startup
      3. 7.3.3 SPI Flash
        1. 7.3.3.1 SPI Flash Interface
        2. 7.3.3.2 SPI Flash Programming
      4. 7.3.4 I2C Interface
      5. 7.3.5 Content Adaptive Illumination Control (CAIC)
      6. 7.3.6 Local Area Brightness Boost (LABB)
      7. 7.3.7 3D Glasses Operation
      8. 7.3.8 Test Point Support
      9. 7.3.9 DMD Interface
        1. 7.3.9.1 Sub-LVDS (HS) Interface
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 PLL Design Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
      1. 9.2.1 56
    3. 9.3 Power-Up Initialization Sequence
    4. 9.4 DMD Fast Park Control (PARKZ)
    5. 9.5 Hot Plug I/O Usage
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PLL Power Layout
      2. 10.1.2 Reference Clock Layout
        1. 10.1.2.1 Recommended Crystal Oscillator Configuration
      3. 10.1.3 Unused Pins
      4. 10.1.4 DMD Control and Sub-LVDS Signals
      5. 10.1.5 Layer Changes
      6. 10.1.6 Stubs
      7. 10.1.7 Terminations
      8. 10.1.8 Routing Vias
      9. 10.1.9 Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
        2. 11.1.2.2 Video Timing Parameter Definitions
    2. 11.2 Related Documentation
    3. 11.3 Related Links
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 用語集
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

7.3.3.1 SPI Flash Interface

The DLPC34xx controller requires an external SPI serial flash memory device to store the firmware. Follow the below guidelines and requirements in addition to the requirements listed in the Flash Interface Timing Requirements section.

The controller supports a maximum flash size of 128 Mb (16 MB). See the DLPC34xx Validated SPI Flash Device Options table for example compatible flash options. The minimum required flash size depends on the size of the utilized firmware. The firmware size depends upon a variety of factors including the number of sequences, lookup tables, and splash images.

The DLPC34xx controller uses a single SPI interface that complies to industry standard SPI flash protocol. The device will begin accessing the flash at a nominal 1.42-MHz frequency before running at a nominal 30-MHz rate. The flash device must support these rates.

The controller has two independent SPI chip select (CS) control lines. Ensure that the chip select pin of the flash device is connects to SPI0_CSZ0 as the controller boot routine is executes from the device connected to chip select zero. The boot routine uploads program code from flash memory to program memory then transfers control to an auto-initialization routine within program memory.

The DLPC34xx is designed to support any flash device that is compatible with the modes of operation, features, and performance as defined in the Additional DLPC34xx SPI Flash Requirements table below Table 7-3, Table 7-4, and Table 7-5.

Table 7-3 Additional DLPC34xx SPI Flash Requirements
FEATUREDLPC34xx REQUIREMENT
SPI interface widthSingle
SPI polarity and phase settingsSPI mode 0
Fast READ addressingAuto-incrementing
Programming modePage mode
Page size256 B
Sector size4-KB sector
Block sizeAny
Block protection bits0 = Disabled
Status register bit(0)Write in progress (WIP), also called flash busy
Status register bit(1)Write enable latch (WEN)
Status register bits(6:2)A value of 0 disables programming protection
Status register bit(7)Status register write protect (SRWP)
Status register bits(15:8)
(that is expansion status byte)		Because the DLPC34xx controller supports only single-byte status register R/W command execution, it may not be compatible with flash devices that contain an expansion status byte. However, as long as the expansion status byte is considered optional in the byte 3 position and any write protection control in this expansion status byte defaults to unprotected, then the flash device is likely compatible with the DLPC34xx.

The DLPC34xx controller is intended to support flash devices with program protection defaults of either enabled or disabled. The controller assumes the default is enabled and proceeds to disable any program protection as part of the boot process.

The DLPC34xx issues these commands during the boot process:

  • A write enable (WREN) instruction to request write enable, followed by
  • A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit
  • After the write enable latch (WEL) bit is set, a write status register (WRSR) instruction that writes 0 to all 8 bits (this disables all programming protection)

Prior to each program or erase instruction, the DLPC34xx controller issues similar commands:

  • A write enable (WREN) instruction to request write enable, followed by
  • A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit
  • After the write enable latch (WEL) bit is set, the program or erase instruction

Note that the flash device automatically clears the write enable status after each program and erase instruction.

Table 7-4 and Table 7-5 below list the specific instruction OpCode and timing compatibility requirements. The DLPC34xx controller does not adapt protocol or clock rate based on the flash type connected.

Table 7-4 SPI Flash Instruction OpCode and Access Profile Compatibility Requirements
SPI FLASH COMMANDBYTE 1
(OPCODE)		BYTE 2BYTE 3BYTE 4BYTE 5BYTE 6
Fast READ (1 output)0x0BADDRS(0)ADDRS(1)ADDRS(2)dummyDATA(0)(1)
Read status0x05N/AN/ASTATUS(0)
Write status0x01STATUS(0)See (2)
Write enable0x06
Page program0x02ADDRS(0)ADDRS(1)ADDRS(2)DATA(0)(1)
Sector erase (4 KB)0x20ADDRS(0)ADDRS(1)ADDRS(2)
Chip erase0xC7
(1) Shows the first data byte only. Data continues.
(2) Access to a second (expansion) write status byte not supported by the DLPC34xx controller.

Table 7-5 below and the Flash Interface Timing Requirements section list the specific timing compatibility requirements for a DLPC34xx compatible flash device.

Table 7-5 SPI Flash Key Timing Parameter Compatibility Requirements
SPI FLASH TIMING PARAMETER(1)(2)SYMBOLALTERNATE SYMBOLMINMAXUNIT
Access frequency (all commands)FRfC≤ 1.4≥ 30.1MHz
Chip select high time (also called chip select deselect time)tSHSLtCSH≤ 200ns
Output hold timetCLQXtHO≥ 0ns
Clock low to output valid timetCLQVtV≤ 11ns
Data in set-up timetDVCHtDSU≤ 5ns
Data in hold timetCHDXtDH≤ 5ns
(1) The timing values apply to the specification of the peripheral flash device, not the DLPC34xx controller. For example, the flash device minimum access frequency (FR) must be 1.4 MHz or less and the maximum access frequency must be 30.1 MHz or greater.
(2) The DLPC34xx does not drive the HOLD or WP (active low write protect) pins on the flash device, and thus these pins must be tied to a logic high on the PCB through an external pullup.

In order for the DLPC34xx controller to support 1.8-V, 2.5-V, or 3.3-V serial flash devices, the VCC_FLSH pin must be supplied with the corresponding voltage. The DLPC34xx Validated SPI Flash Device Options table contains a list of validated 1.8-V, 2.5-V, or 3.3-V compatible SPI serial flash devices supported by the DLPC34xx controller.

Table 7-6 DLPC34xx Validated SPI Flash Device Options(1)(2)(3)
DENSITY (Mb)VENDORPART NUMBERPACKAGE SIZE
1.8-V COMPATIBLE DEVICES
4 MbWinbondW25Q40BWUXIG2 × 3 mm USON
4 MbMacronixMX25U4033EBAI-12G1.43 × 1.94 mm WLCSP
8 MbMacronixMX25U8033EBAI-12G1.68 × 1.99 mm WLCSP
2.5- OR 3.3-V COMPATIBLE DEVICES
16 MbWinbondW25Q16CLZPIG5 × 6 mm WSON
(1) The flash supply voltage must equal VCC_FLSH supply voltage on the DLPC34xx controller. Make sure to order the device that supports the correct supply voltage as multiple voltage options are often available.
(2) Numonyx (Micron) serial flash devices typically do not support the 4 KB sector size compatibility requirement for the DLPC34xx controller.
(3) The flash devices in this table have been formally validated by TI. Other flash options may be compatible with the DLPC34xx controller, but they have not been formally validated by TI.