JAJSEP0F
April 2013 – May 2019
DLPC350
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
アプリケーション概略図
4
改訂履歴
5
概要(続き)
6
Pin Configuration and Functions
Pin Functions
Table 1.
Power and Ground Pin Descriptions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
I/O Electrical Characteristics
7.6
I2C0 and I2C1 Interface Timing Requirements
7.7
Port 1 Input Pixel Interface Timing Requirements
7.8
Port 2 Input Pixel Interface (FPD-Link Compatible LVDS Input) Timing Requirements
7.9
System Oscillator Timing Requirements
7.10
Reset Timing Requirements
7.11
Video Timing Input Blanking Specification
7.11.1
Source Input Blanking
7.12
Programmable Output Clocks Switching Characteristics
7.13
DMD Interface Switching Characteristics
7.14
JTAG Interface: I/O Boundary Scan Application Switching Characteristics
8
Parameter Measurement Information
8.1
Power Consumption
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Board Level Test Support
9.4
Device Functional Modes
9.4.1
Structured Light Applications
9.4.2
(LVDS) Receiver Supported Pixel Mapping Modes
10
Application and Implementation
10.1
Application Information
10.2
Typical Applications
10.2.1
Typical Chipset Application
10.2.1.1
Design Requirements
10.2.1.2
Detailed Design Procedure
10.2.1.2.1
DLPC350 System Interfaces
10.2.1.2.1.1
Control Interface
10.2.1.2.1.2
Input Data Interface
10.2.1.2.2
DLPC350 System Output Interfaces
10.2.1.2.2.1
Illumination Interface
10.2.1.2.2.2
Trigger Interface (Sync Outputs)
10.2.1.2.3
DLPC350 System Support Interfaces
10.2.1.2.3.1
Reference Clock
10.2.1.2.3.2
PLL
10.2.1.2.3.3
Program Memory Flash Interface
10.2.1.2.4
DMD Interfaces
10.2.1.2.4.1
DLPC350 to DMD Digital Data
10.2.1.2.4.2
DLPC350 to DMD Control Interface
10.2.1.2.4.3
DLPC350 to DMD Micromirror Reset Control Interface
11
Power Supply Recommendations
11.1
System Power and Reset
11.1.1
Default Conditions
11.1.1.1
1.2-V System Power
11.1.1.2
1.8-V System Power
11.1.1.3
1.9-V System Power
11.1.1.4
3.3-V System Power
11.1.1.5
FPD-Link Input LVDS System Power
11.1.2
System Power-up and Power-down Sequence
11.1.3
Power-On Sense (POSENSE) Support
11.1.4
Power-Good (PWRGOOD) Support
11.1.5
5-V Tolerant Support
11.1.6
Power Reset Operation
11.1.7
System Reset Operation
12
Layout
12.1
Layout Guidelines
12.1.1
DMD Interface Design Considerations
12.1.2
DMD Termination Requirements
12.1.3
Decoupling Capacitors
12.1.4
Power Plane Recommendations
12.1.5
Signal Layer Recommendations
12.1.6
General Handling Guidelines for CMOS-Type Pins
12.1.7
PCB Manufacturing
12.1.7.1
General Guidelines
12.1.7.2
Trace Widths and Minimum Spacings
12.1.7.3
Routing Constraints
12.1.7.4
Fiducials
12.1.7.5
Flex Considerations
12.1.7.6
DLPC350 Thermal Considerations
12.2
Layout Example
12.2.1
Printed Circuit Board Layer Stackup Geometry
12.2.2
Recommended DLPC350 MOSC Crystal Oscillator Configuration
12.2.3
Recommended DLPC350 PLL Layout Configuration
13
デバイスおよびドキュメントのサポート
13.1
デバイス・サポート
13.1.1
ビデオ・タイミング・パラメータの定義
13.1.2
デバイスの項目表記
13.1.3
デバイス・マーキング
13.2
ドキュメントのサポート
13.2.1
関連資料
13.3
商標
13.4
Glossary
14
メカニカル、パッケージ、および注文情報
14.1
Package Option Addendum
14.1.1
Packaging Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
ZFF|419
MPBGAF9
サーマルパッド・メカニカル・データ
10.2
Typical Applications