JAJSLD1C May   2021  – November 2022 DLPC6540

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  DMD HSSI Electrical Characteristics
    8. 6.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 6.9  V-by-One Interface Electrical Characteristics
    10. 6.10 USB Electrical Characteristics
    11. 6.11 System Oscillator Timing Requirements
    12. 6.12 Power Supply and Reset Timing Requirements
    13. 6.13 DMD HSSI Timing Requirements
    14. 6.14 DMD Low-Speed LVDS Timing Requirements
    15. 6.15 V-by-One Interface General Timing Requirements
    16. 6.16 Source Frame Timing Requirements
    17. 6.17 Synchronous Serial Port Interface Timing Requirements
    18. 6.18 Master and Slave I2C Interface Timing Requirements
    19. 6.19 Programmable Output Clock Timing Requirements
    20. 6.20 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    21. 6.21 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    22. 6.22 Multi-Trace ETM Interface Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sources
      2. 7.3.2 Processing Delays
      3. 7.3.3 V-by-One Interface
      4. 7.3.4 DMD (HSSI) Interface
      5. 7.3.5 Program Memory Flash Interface
      6. 7.3.6 GPIO Supported Functionality
      7. 7.3.7 Debug Support
    4. 7.4 Device Operational Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Normal Configuration
  8. 8 Power Supply Recommendations
    1. 8.1 Power Supply Management
    2. 8.2 Hot Plug Usage
    3. 8.3 Power Supplies for Unused Input Source Interfaces
    4. 8.4 Power Supplies
      1. 8.4.1 1.15-V Power Supplies
      2. 8.4.2 1.21V Power Supply
      3. 8.4.3 1.8-V Power Supplies
      4. 8.4.4 3.3-V Power Supplies
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 General Layout Guidelines
      2. 9.1.2 Power Supply Layout Guidelines
      3. 9.1.3 Layout Guidelines for Internal Controller PLL Power
      4. 9.1.4 Layout Guideline for DLPC6540 Reference Clock
        1. 9.1.4.1 Recommended Crystal Oscillator Configuration
      5. 9.1.5 V-by-One Interface Layout Considerations
      6. 9.1.6 USB Interface Layout Considerations
      7. 9.1.7 DMD Interface Layout Considerations
      8. 9.1.8 General Handling Guidelines for Unused CMOS-Type Pins
      9. 9.1.9 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 9.2 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings
        2. 10.1.2.2 Package Data
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
      1. 10.6.1 Video Timing Parameter Definitions
  11. 11Mechanical, Packaging, and Orderable Information
    1.     79

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.12 Power Supply and Reset Timing Requirements

PARAMETER MIN MAX UNIT
tRAMP-UP Power supply ramp-up time.(1) Figure 6-5 Power supply ramp for each supply
Ramp-up time: TOV × 10% to TOV × 90%
TOV = Typical Operational Voltage		 0.01 10 ms
tRAMP-UP-TOTAL Total power supply ramp-up time.(1) Total time within which the 1.15-V, 1.8-V, 1.21-V, and 3.3-V supplies must complete their ramp-up from the start of the 1.15-V ramp-up.
Ramp-up time: TOV × 10% to TOV × 90%
TOV = Typical Operational Voltage		 100 ms
tRAMP-DOWN Power supply ramp-down time. (1) Figure 6-5 Figure 6-6 Power supply ramp for each supply
Ramp-down time: TOV × 90% to TOV × 10%
TOV = Typical Operational Voltage		 0 100 ms
tRAMP-DOWN-TOTAL Total power supply ramp-down time.(1) Total time within which the 1.15-V, 1.8-V, 1.21-V, and 3.3-V supplies must complete their ramp-down from the start of the 3.3-V ramp-up.
Ramp-down time: TOV × 90% to TOV × 10%
TOV = Typical Operational Voltage		 100 ms
tRUSD18 1.8-V Supply Ramp-up Start Delay (2) Figure 6-6 Delay from 1.15-V supply ramp start to 1.8-V supply ramp start. See (3) ms
tRUSD33 3.3-V Supply Ramp-up Start Delay (2) Figure 6-6 Delay from 1.15-V supply ramp start to 3.3-V supply ramp start 10 50 ms
tRUSD12 1.21-V Supply Ramp-up Start Delay (2) Figure 6-6 Delay from 1.8-V supply ramp start to 1.21-V supply ramp start. See (4) ms
tRDSD18 1.8-V Supply Ramp-down Start Delay (2) Figure 6-6 Delay from 1.21-V supply ramp start to 1.8-V supply ramp start. See (5) ms
tRDSD115 1.15-V Supply Ramp-down Start Delay (2) Figure 6-6 Delay from 3.3-V supply ramp start to 1.15-V supply ramp start. See(8)
tEW Early Warning Time Figure 6-8 PWRGOOD goes inactive low (as an early warning) prior to any power supply voltage going below the controller specification 500 µs
tPH Power Hold Time Figure 6-8 POSENSE remains active after PWRGOOD is disabled 500(9) µs
tw1 Pulse duration, in-active low, PWRGOOD Figure 6-7 PWRGOOD inactive time while POSENSE is active
50% to 50% reference points (signal)		 4 1000 (6) µs
tt1 Transition time, PWRGOOD
tt1 = tƒ1 and tr1
Figure 6-7		 Rise and Fall time for PWRGOOD
20% to 80% reference points (signal)		 625 µs
tw2 Pulse duration, in-active low, POSENSE Figure 6-8 POSENCE inactive time while PWRGOOD is inactive
50% to 50% reference points (signal)		 100 ms
tt2 Transition time, POSENSE
tt1 = tƒ1 and tr1
Figure 6-8		 Rise and Fall time for POSENSE (7)
20% to 80% reference points (signal)		 25 µs
tPSD PWRGOOD Start Delay Figure 6-7 Time after rising edge of POSENSE before PWRGOOD effects DLPC6540 operation 51.5 60 ms
tPROJ_ON PROJ_ON fall time delay to PWRGOOD Figure 6-8 Fall Delay
PROJ_ON 80% to PWRGOOD 80% fall time start		 10 ms
tREFCLKA Time to stable REFCLKA Figure 6-7 Time to stable REFLCKA before POSENSE See (10)
(1) It is assumed that all 1.15-V supplies come from the same source, although some can have additional filtering before entering the DLPC6540. As such, it is expected these supplies to ramp together (aside from differences caused by filtering). This same expectation is true for the 1.21-V, 1.8-V, and 3.3-V supplies.
(2) The DLPC6540 has specific power supply sequencing requirements, listed below, that include the timings specified in this table.
  1. Power Up Order:
    1. 1.15-V (Core, Analog) » 1.8-V (I/O, SCS) » 1.21-V (SCS)
    2. 1.15-V (Core, Analog) » 3.3-V (I/O
  2. Power Down Order:
    1. 3.3-V (I/O) » 1.15-V (Core, Analog)
    2. 1.21-V (SCS) » 1.8-V (I/O, SCS) » 1.15-V (Core, Analog)
(3) This delay requirement parameter is defined as the time between two events. The first event is the point where the 1.15-V power supply ramp-up is started, and the second event is when the 1.15-V supply ramp-up reaches 80% of TOV (at which point the 1.8-V supply can start its ramp-up). Because the occurrence of the second event depends on the specific design of the 1.15-V power supply, the designer must determine the specific delay time.
(4) This delay requirement parameter is defined as the time between two events. The first event is the point where the 1.8-V power supply ramp-up is started, and the second event is when the 1.8-V supply ramp-up reaches 80% of TOV (at which point the 1.21-V supply can start its ramp-up). Because the occurrence of the second event depends on the specific design of the 1.8-V power supply, the designer must determine the specific delay time.
(5) This delay requirement parameter is defined as the time between two events. The first event is the point where the 1.21-V power supply ramp-down is started, and the second event is when the 1.21-V supply ramp-down reaches 20% of TOV (at which point the 1.8-V supply can start its ramp-down). Because the occurrence of the second event depends on the specific design of the 1.21-V power supply, the designer must determine the specific delay time. The intent of this delay time is to guarantee that the voltage level of the 1.8-V supply never falls lower than the voltage level of the 1.21-V supply during the ramp-down until the 1.2-V supply is below 300 mV.
(6) This max value is only applicable if the 1.8-V power remains ON while PWRGOOD is inactive. Otherwise, there is no maximum limit.
(7) As long as noise on this signal is below the hysteresis threshold
(8) This delay requirement parameter is defined as the time between two events. The first event is the point where the 3.3-V power supply ramp-down is started, and the second event is when the 3.3-V supply ramp-down and 1.8-V supply ramp down reaches 10% of TOV (at which point the 1.15-V supply can start its ramp-down). Because the occurrence of the second event depends on the specific design of the 3.3-V and 1.8-V power supply, the designer must determine the specific delay time.
(9) If PROJ_ON is used for power down then Power Hold Time (tPH) is not required.
(10) This delay requirement parameter is defined by design of RECLKA oscillator. Stable clock must be provided before releasing POSENSE.
GUID-C4373E1D-FB3C-4D2C-8D02-7366D43374DE-low.gif Figure 6-5 Power Supply Ramp Time
GUID-20210202-CA0I-XM6V-BCQN-K4M9NFPZDDS6-low.gif Figure 6-6 Power Supply Ramp Sequencing Profiles
GUID-20210204-CA0I-WQWM-K5KJ-Z2J7PTFXN3NV-low.gif Figure 6-7 Power Up Timing
Figure 6-8 Power Down Timing—Normal
Figure 6-9 Power Down Timing—Fault