JAJSLD1C May 2021 – November 2022 DLPC6540
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX(1) | UNIT | |
---|---|---|---|---|---|---|
V(VDD115) | 1.15-V Power | Maximum current at VDD115 = 1.2 V | 5640 | mA | ||
V(VDD115_PLLMA) (Core) | 1.15-V Digital Power MCG-A PLL (Master Clock Generator) | Maximum current at VDD115_PLLMA = 1.2 V | 6 | mA | ||
V(VDD115_PLLMB) (Core) | 1.15-V Digital Power MCG-B PLL (Master Clock Generator) | Maximum current at VDD115_PLLMB = 1.2 V | 6 | mA | ||
V(VDD115_PLLS) (Core) | 1.15-V Analog Power SCG Doubler PLL | Maximum current at VDD115_PLLS = 1.2 V | 3 | mA | ||
V(VAD115_FPD) (Core) (2) | 1.15-V Analog Power FPD | Maximum current at VAD115_FPD = 1.2 V Ports A and B Active, Port C inactive | 99 | mA | ||
V(VAD115_VX1) (Core) (2) | 1.15-V Analog Power VX1 | Maximum current at VAD115_VX1 = 1.2 V 8 Lanes, with total BW = 3.0Gbps) | 400 | mA | ||
V(VAD115_HSSI) (Core) | 1.15-V Digital Power HSSI | Maximum current at VDD115_HSSI = 1.2 V Both ports active | 462 | mA | ||
V(VAD115_HSSI0_PLL) (Core) | 1.15-V Digital Power HSSI0 PLL | Maximum current at VDD115_HSSI0_PLL = 1.2 V Both ports active | 1 | mA | ||
V(VAD115_HSSI1_PLL) (Core) | 1.15-V Digital Power HSSI1 PLL | Maximum current at VDD115_HSSI1_PLL = 1.2 V Both ports active | 1 | mA | ||
V(VDD121_SCS) (Core) | 1.21V Digital Power SCS DRAM | Maximum current at VDD121_SCS = 1.30 V | 334 | mA | ||
V(VAD18_PLLMA) (Core) | 1.8-V Analog Power MCG-A PLL (Master Clock Generator) | Maximum current at VAD18_PLLMA = 1.89 V | 10 | mA | ||
V(VAD18_PLLMB) (Core) | 1.8-V Analog Power MCG-B PLL (Master Clock Generator) | Maximum current at VAD18_PLLMB = 1.89 V | 10 | mA | ||
V(VAD18_VX1) (I/O) (2) | 1.8-V Analog Power VX1 Interface | Maximum current at VAD18_VX1 = 1.89 V 8 Lanes, with total BW = 3.0Gbps | 41 | mA | ||
V(VDD18_SCS) (Core) | 1.8-V Digital Power SCS DRAM | Maximum current at VDD18_SCS = 1.89 V | 327 | mA | ||
V(VDD18_LVDS) (I/O) | 1.8-V Analog Power DMD LS Interface | Maximum current at VDD18_LVDS = 1.89 V | 31 | mA | ||
V(VDD33) (I/O) | 3.3-V Digital Power - (All 3.3-V I/O without dedicated 3.3-V supply - e.g. GPIO) | Maximum current at VDD33 = 3.3456 V | 28 | mA | ||
V(VAD33_OSCA) (I/O) | 3.3-V Analog Power Crystal/OSCA Interface | Maximum current at VDD33_OSCA = 3.3456 V | 5 | mA | ||
V(VAD33_OSCB) (I/O) | 3.3-V Analog Power Crystal-OSCB Interface | Maximum current at VDD33_OSCB =3.3456 V | 5 | mA | ||
V(VDD33_FPD) (I/O) (2) | 3.3-V Digital Power FPD interface | Maximum current at VDD33_FPD = 3.3456 V Ports A and B Active, Port C inactive | 102 | mA | ||
V(VAD33_USB) (I/O) | 3.3-V Analog Power USB Interface | Maximum current at VDD33_USB =3.3456 V | 78 | mA | ||
V(VDD33_HSSI) (I/O) | 3.3-V Digital Power DMD HSSI Interface | Maximum current at VDD33_HSSI = 3.3456 V Both ports active, with total BW = 3.0Gbps | 194 | mA |