JAJSLD1C May   2021  – November 2022 DLPC6540

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  DMD HSSI Electrical Characteristics
    8. 6.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 6.9  V-by-One Interface Electrical Characteristics
    10. 6.10 USB Electrical Characteristics
    11. 6.11 System Oscillator Timing Requirements
    12. 6.12 Power Supply and Reset Timing Requirements
    13. 6.13 DMD HSSI Timing Requirements
    14. 6.14 DMD Low-Speed LVDS Timing Requirements
    15. 6.15 V-by-One Interface General Timing Requirements
    16. 6.16 Source Frame Timing Requirements
    17. 6.17 Synchronous Serial Port Interface Timing Requirements
    18. 6.18 Master and Slave I2C Interface Timing Requirements
    19. 6.19 Programmable Output Clock Timing Requirements
    20. 6.20 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    21. 6.21 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    22. 6.22 Multi-Trace ETM Interface Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sources
      2. 7.3.2 Processing Delays
      3. 7.3.3 V-by-One Interface
      4. 7.3.4 DMD (HSSI) Interface
      5. 7.3.5 Program Memory Flash Interface
      6. 7.3.6 GPIO Supported Functionality
      7. 7.3.7 Debug Support
    4. 7.4 Device Operational Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Normal Configuration
  8. 8 Power Supply Recommendations
    1. 8.1 Power Supply Management
    2. 8.2 Hot Plug Usage
    3. 8.3 Power Supplies for Unused Input Source Interfaces
    4. 8.4 Power Supplies
      1. 8.4.1 1.15-V Power Supplies
      2. 8.4.2 1.21V Power Supply
      3. 8.4.3 1.8-V Power Supplies
      4. 8.4.4 3.3-V Power Supplies
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 General Layout Guidelines
      2. 9.1.2 Power Supply Layout Guidelines
      3. 9.1.3 Layout Guidelines for Internal Controller PLL Power
      4. 9.1.4 Layout Guideline for DLPC6540 Reference Clock
        1. 9.1.4.1 Recommended Crystal Oscillator Configuration
      5. 9.1.5 V-by-One Interface Layout Considerations
      6. 9.1.6 USB Interface Layout Considerations
      7. 9.1.7 DMD Interface Layout Considerations
      8. 9.1.8 General Handling Guidelines for Unused CMOS-Type Pins
      9. 9.1.9 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 9.2 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings
        2. 10.1.2.2 Package Data
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
      1. 10.6.1 Video Timing Parameter Definitions
  11. 11Mechanical, Packaging, and Orderable Information
    1.     79

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.16 Source Frame Timing Requirements

See Figure 6-14
PARAMETER (1)MINMAXUNIT
tp_vswVSYNC Active Pulse Width50% reference points1127lines
tp_vbpVertical back porch (VBP) (2)50% reference points2 (3)lines
tp_vƒpVertical front porch (VFP) (2)50% reference pointsMAX[ (TVBMIN - 65 ), 1] (3)lines
tp_tvbTotal vertical blanking (TVB) (2)50% reference pointsSee (4)lines
tp_hswHSYNC Active Pulse Width50% reference points16PCLKs
tp_hbpHorizontal back porch (HBP) (5)50% reference points5 (Digital Video Sources)
65 (Analog Video Sources)		PCLKs
tp_hfpHorizontal front porch (HFP) (5)50% reference points2PCLKs
tp_thbTotal horizontal blanking (THB) (5)50% reference points20 (Digital Video Sources)
80 (Analog Video Sources) (6)		PCLKs
flineHorizontal line rate37.354K Hz
APPLActive Pixels per Line6404096Pixels
ALPFActive Lines per Frame480 2160 (Normal)Lines
(1) The requirements in the table apply to all external sources
(2) Vertical Blanking Parameter Definitions:
  1. Vertical Back Porch: Time from the leading edge of VSYNC to the leading edge of HSYNC for the first active line, and includes the VSYNC pulse width tp_vsw.
  2. Vertical Front Porch: Time from the leading edge of HSYNC following the last active line in a frame to the leading edge of VSYNC
  3. Total Vertical Blanking: The sum of VBP + VFP = TVB.
(3) The vertical blanking required (per TVB) can be allocated as desired as long as the VFP and VBP minimum values are met.
(4) The minimum TVB can be calculated using the following:
TVBmin = 11 + ROUNDUP(LLS_VFP_MIN × (Source_ALPF/VPS_ALPF)), where:
  1. LLS_VFP_MIN (Normal Mode) = 22
  2. Source_ALPF = Active Lines Per Frame of the incoming source
  3. VPS_ALPF = 1080 (for 1920x1080 Native products and 3840x2160 4-way XPR products)
  4. Less TVBmin blanking can be required depending on the video processing being done. The configurations that drive the worst case minimum value are those configurations that combine the maximum (or near maximum) capabilities of functions such as scaling, warping, and keystone correction.
  5. This is applicable to all sources (Section 7.4). Other sources require directed testing in the end application.
  6. The minimum recommended TVB with CVT 1.2 sources is 23.
(5) Horizontal Blanking Parameter Definitions:
  1. Horizontal Back Porch: Time from the leading edge of HSYNC to the rising edge of DATEN, and includes the HSYNC pulse width tp_hsw.
  2. Horizontal Front Porch: Time from the falling edge of DATEN to the leading edge of HSYNC.
  3. Total Horizontal Blanking: The sum of HBP + HFP = THB.
(6) The horizontal blanking required (per THB) can be allocated as desired as long as the HFP and HBP minimum values are met.
GUID-CE3CB68B-F2BD-4BA4-94F5-60CAFE07292F-low.gifFigure 6-14 Source Frame Timing