JAJSLD1C
May 2021 – November 2022
DLPC6540
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Power Electrical Characteristics
6.6
Pin Electrical Characteristics
6.7
DMD HSSI Electrical Characteristics
6.8
DMD Low-Speed LVDS Electrical Characteristics
6.9
V-by-One Interface Electrical Characteristics
6.10
USB Electrical Characteristics
6.11
System Oscillator Timing Requirements
6.12
Power Supply and Reset Timing Requirements
6.13
DMD HSSI Timing Requirements
6.14
DMD Low-Speed LVDS Timing Requirements
6.15
V-by-One Interface General Timing Requirements
6.16
Source Frame Timing Requirements
6.17
Synchronous Serial Port Interface Timing Requirements
6.18
Master and Slave I2C Interface Timing Requirements
6.19
Programmable Output Clock Timing Requirements
6.20
JTAG Boundary Scan Interface Timing Requirements (Debug Only)
6.21
JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
6.22
Multi-Trace ETM Interface Timing Requirements
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Input Sources
7.3.2
Processing Delays
7.3.3
V-by-One Interface
7.3.4
DMD (HSSI) Interface
7.3.5
Program Memory Flash Interface
7.3.6
GPIO Supported Functionality
7.3.7
Debug Support
7.4
Device Operational Modes
7.4.1
Standby Mode
7.4.2
Active Mode
7.4.2.1
Normal Configuration
8
Power Supply Recommendations
8.1
Power Supply Management
8.2
Hot Plug Usage
8.3
Power Supplies for Unused Input Source Interfaces
8.4
Power Supplies
8.4.1
1.15-V Power Supplies
8.4.2
1.21V Power Supply
8.4.3
1.8-V Power Supplies
8.4.4
3.3-V Power Supplies
9
Layout
9.1
Layout Guidelines
9.1.1
General Layout Guidelines
9.1.2
Power Supply Layout Guidelines
9.1.3
Layout Guidelines for Internal Controller PLL Power
9.1.4
Layout Guideline for DLPC6540 Reference Clock
9.1.4.1
Recommended Crystal Oscillator Configuration
9.1.5
V-by-One Interface Layout Considerations
9.1.6
USB Interface Layout Considerations
9.1.7
DMD Interface Layout Considerations
9.1.8
General Handling Guidelines for Unused CMOS-Type Pins
9.1.9
Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
9.2
Thermal Considerations
10
Device and Documentation Support
10.1
Device Support
10.1.1
Third-Party Products Disclaimer
10.1.2
Device Nomenclature
10.1.2.1
Device Markings
10.1.2.2
Package Data
10.2
Receiving Notification of Documentation Updates
10.3
サポート・リソース
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
10.6.1
Video Timing Parameter Definitions
11
Mechanical, Packaging, and Orderable Information
79
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
ZDC|676
MPBGAP5
サーマルパッド・メカニカル・データ
発注情報
jajsld1c_oa
10.1
Device Support