JAJSLD1 データシート

JAJSLD1C May 2021 – November 2022 DLPC6540

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

ZDC|676
- MPBGAP5

サーマルパッド・メカニカル・データ

発注情報

jajsld1c_oa

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

PARAMETER		TOLERANCE	MIN	NOM	MAX	UNIT
V_(VDD115) (Core)	1.15-V Power	± 4.35% tolerance	1.10	1.15	1.20	V
V_{(VDD115_PLLMA)} (Core)	1.15-V Digital Power - MCG-A PLL (Master Clock Generator)	+4.35/-9.13% tolerance	1.045	1.15	1.20	V
V_{(VDD115_PLLMB)} (Core)	1.15-V Digital Power - MCG-B PLL (Master Clock Generator)	+4.35/-9.13% tolerance	1.045	1.15	1.20	V
V_{(VDD115_PLLS)} (Core)	1.15-V Analog Power - SCG Doubler PLL	+4.35/-9.13% tolerance	1.045	1.15	1.20	V
V_{(VAD115_FPD)} (Core)	1.15-V Analog Power - FPD	+4.35/-9.13% tolerance	1.045	1.15	1.20	V
V_{(VAD115_VX1)} (Core)	1.15-V Analog Power - VX1	+4.35/-9.13% tolerance	1.045	1.15	1.20	V
V_{(VAD115_HSSI)} (Core)	1.15-V Analog Power - HSSI	+4.35/-9.13% tolerance	1.045	1.15	1.20	V
ΔV_{(VAD115_HSSI)} (Core)	pk-pkVAD115_HSSI supply noise @ 10 MHz (sine)				20	mV
V_{(VAD115_HSSI0_PLL)} (Core)	1.15-V Analog Power - HSSI0 PLL	+4.35/-9.13% tolerance	1.045	1.15	1.20	V
ΔV_{(VAD115_HSSI0_PLL)} (Core)	pk-pkVAD115_HSSI0_PLL supply noise @ 10 MHz (sine)				20	mV
V_{(VAD115_HSSI1_PLL)} (Core)	1.15-V Analog Power - HSSI1 PLL	+4.35/-9.13% tolerance	1.045	1.15	1.20	V
ΔV_{(VAD115_HSSI1_PLL)} (Core)	pk-pkVAD115_HSSI1_PLL supply noise @ 10 MHz (sine)				20	mV
V_{(VDD121_SCS)} (Core)	1.21V Digital Power - SCS DRAM	+7.43/-4.95% tolerance	1.15	1.21	1.30	V
V_{(VAD18_PLLMA)} (Core)	1.8-V Analog Power - MCG-A PLL (Master Clock Generator)	±5.0% tolerance	1.71	1.80	1.89	V
V_{(VAD18_PLLMB)} (Core)	1.8-V Analog Power - MCG-B PLL (Master Clock Generator)	±5.0% tolerance	1.71	1.80	1.89	V
V_{(VAD18_VX1)} (I/O)	1.8-V Analog Power - VX1 Interface	±5.0% tolerance	1.71	1.80	1.89	V
V_{(VDD18_SCS)} (Core)	1.8-V Digital Power - SCS DRAM	±5.0% tolerance	1.71	1.80	1.89	V
V_{(VDD18_LVDS)} (I/O)	1.8-V Analog Power - DMD LS Interface	±5.0% tolerance	1.71	1.80	1.89	V
V_(VDD33) (I/O)	3.3-V Digital Power - (All 3.3-V I/O without dedicated 3.3-V supply - e.g. GPIO)	±5.0% tolerance	3.135	3.3	3.465	V
V_{(VAD33_OSCA)} (I/O)	3.3-V Analog Power - Crystal-OSCA Interface	±5.0% tolerance	3.135	3.3	3.465	V
V_{(VAD33_OSCB)} (I/O)	3.3-V Analog Power - Crystal-OSCB Interface	±5.0% tolerance	3.135	3.3	3.465	V
V_{(VDD33_FPD)} (I/O)	3.3-V Digital Power - FPD interface	±5.0% tolerance	3.135	3.3	3.465	V
V_{(VAD33_USB)} (I/O)	3.3-V Analog Power - USB Interface	±5.0% tolerance	3.135	3.3	3.465	V
V_{(VDD33_HSSI)} (I/O)	3.3-V Digital Power - DMD HSSI Interface	±5.0% tolerance	3.135	3.3	3.465	V
ΔV_{(VDD33_HSSI)} (I/O)	pk-pkVDD33_HSSI supply noise @ 10 MHz (sine)				60	mV
GENERAL
T_J	Operating junction temperature		0		115	°C
T_C	Operating case temperature		0		108	°C
T_A	Operating ambient temperature ⁽¹⁾⁽²⁾		0		55	°C

(1) The operating ambient temperature range values were determined based on the board design parameters described in Section 9.1.1 , rather than using a JEDEC JESD51 standard test card and environment, along with min and max estimated power dissipation across process, voltage, and temperature. Ambient thermal conditions, which impact R_θJA, vary by application. Thus, maximum operating ambient temperature varies by application.

T_{a_min} = T_{j_min} – (P_{d_min} × R_θJA) = 0°C – (host_min_valueW × host_value°C/W) = –host_calculated_value°C
T_{a_max} = T_{j_max} – (P_{d_max} × R_θJA) = +115°C – (host_max_valueW × host_value°C/W) = +host_calculated_value°C

(2) Operating ambient temperature is dependent on system thermal design. Operating case temperature cannot exceed its specified range across ambient temperature conditions.